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Index > Main > cases of mandatory usage of memory fences

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sylware



Joined: 23 Oct 2020
Posts: 161
Location: Marseille/France
sylware
Out-of-order x64 CPUs have cases when memory fences are mandatory.

... and I unable to find them again in AMD/Intel assembly programming manuals.

Anybody?
Post 18 Jul 2022, 20:08
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bitRAKE



Joined: 21 Jul 2003
Posts: 3489
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bitRAKE
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/memory-barriers.txt wrote:
AMD64 Architecture Programmer's Manual Volume 2: System Programming
    Chapter 7.1: Memory-Access Ordering
    Chapter 7.4: Buffering and Combining Memory Writes

IA-32 Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide
    Chapter 7.1: Locked Atomic Operations
    Chapter 7.2: Memory Ordering
    Chapter 7.4: Serializing Instructions

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Post 18 Jul 2022, 22:35
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sylware



Joined: 23 Oct 2020
Posts: 161
Location: Marseille/France
sylware
I was in the wrong AMD64 manual... jez...

ok, thx!

And, yes reads can happen before prior writes if not in the same location.
Post 19 Jul 2022, 02:19
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