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Index > Main > new way to write spin locks on latest x86_64

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sylware



Joined: 23 Oct 2020
Posts: 231
Location: Marseille/France
sylware 18 Jun 2022, 12:37
Hi,

I don't know why, I cannot find it again in intel/amd documentation, but I pretty sure I read something about how to implement more efficiently a spin lock on latest x86_64 archs.

Anyone less lame than me who knows where the info is ?

I'll probably patch the code "paragraphs" where my spin locks will be.
Post 18 Jun 2022, 12:37
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Furs



Joined: 04 Mar 2016
Posts: 2020
Furs 18 Jun 2022, 14:14
I only know the pause instruction that hints the CPU it's in a spinlock. Use it in the loop.

Also when you read the memory in a spinlock, do it without lock prefix. Do a normal read so you don't congest the bus. Once your read is satisfied correctly, then do the whole locked thing and verify again. You can't trust the results from the normal read, it's there just to avoid locking all the time.
Post 18 Jun 2022, 14:14
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sylware



Joined: 23 Oct 2020
Posts: 231
Location: Marseille/France
sylware 18 Jun 2022, 15:20
yep, I found it in AMD documentation using the right keywords.

It is exactly that.

That said, when in the loops would you use the pause instruction?

spinlock linux code (linus tree) is the product of "not very sane" (to stay polite) minds (something is clearly wrong with them, wonder how they could commit anything to the linux tree).
Post 18 Jun 2022, 15:20
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Ali.Z



Joined: 08 Jan 2018
Posts: 535
Ali.Z 18 Jun 2022, 20:01
Intel wrote:
Code:
Spin_Lock:
CMP lockvar, 0 ; // Check if lock is free.
JE  Get_lock
PAUSE;                    // Short delay.
JMP Spin_Lock;
Get_Lock:
MOV EAX, 1;
XCHG EAX, lockvar; // Try to get lock.
CMP EAX, 0;              // Test if successful.
JNE Spin_Lock;
Critical_Section:
<critical section code>
MOV lockvar, 0;          // Release lock.    

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Post 18 Jun 2022, 20:01
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Furs



Joined: 04 Mar 2016
Posts: 2020
Furs 19 Jun 2022, 14:48
Yep like Ali.Z posted, though you'll probably find using lock cmpxchg a lot more often since it's much more flexible. Depending on what kind of locking mechanism you need. Note that normal xchg has implicit lock prefix on memory operand, so the above does in fact that a lock on the bus.

BTW it should be [lockvar] since you're addressing the memory, not its address.
Post 19 Jun 2022, 14:48
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sylware



Joined: 23 Oct 2020
Posts: 231
Location: Marseille/France
sylware 19 Jun 2022, 15:33
yeah, I think I am going to use lock cmpxchg.
Post 19 Jun 2022, 15:33
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Ali.Z



Joined: 08 Jan 2018
Posts: 535
Ali.Z 19 Jun 2022, 18:23
Furs wrote:
BTW it should be [lockvar] since you're addressing the memory, not its address.

Yes I know, but this is a copy-paste from Intel (C inline assembly example); I did not write it.

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Post 19 Jun 2022, 18:23
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sylware



Joined: 23 Oct 2020
Posts: 231
Location: Marseille/France
sylware 20 Jun 2022, 13:47
I thank you all for you help.
Post 20 Jun 2022, 13:47
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