Fasm 1.73
cmp work with dword in 64 bits ?

I guess, you need a register, mov is the only instruction for load a 64 bits literal.

Like this:

cmp qword [rsi],rax

possible is negative value

that because intel architecture is not fully 64-bit, i believe last year or last two years intel expanded their bus from 48-bits to 54-bits.

The x86-64 architecture instructions were designed by AMD, though.

ALU is 64-bit, address space is canonical to the implemented bus lines.
https://stackoverflow.com/questions/25852367/x86-64-canonical-address

Internally the x86-64 architecture is fully 64-bit.

But the instruction encoding doesn't have allowance for 64-bit constants except for MOV REG,IMM64.

The external address bus is not related to the internal bitness in any way. The address bus can be narrower or wider than the internal bitness. 32-bit CPUs have had a 24-bit, 32-bit, 36-bit or 40-bit external address bus.

Also the external data bus doesn't necessarily match the internal bitness either. 32-bit CPUs have had 16-bit, 32-bit or 64-bit external data buses. And 16-bit CPUs have had 8-bit or 16-bit data buses. The latest batch of 64-bit CPUs can have narrower or wider data buses also.

Note the the existence of XMM, YMM, etc. with the wide registers doesn't mean the CPU is 128-bit or 256-bit etc. It is still a 64-bit architecture.

It turns out that I have a 128-bit compare macro in my support algorithms. Not that it's difficult to code - just being complete in response to the thread. Using a similar method one can create a macro to perform all kinds of extended operations with immediate data. fasmg makes this incredibly easy.

I like the graphic in the wiki article.