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Hotwire



Joined: 17 Sep 2015
Posts: 1
Hotwire
Hello!
I’ve recently looked through latest fasm manual and was very excited that amount of xmm-registers is doubled but I found pretty hard to find information about accessing those additional registers. Traditional instructions like
addps xmm0,xmm31
are failed to compile.

Links with helpful information are very welcome

P.S. AVX examples from standard windows distributive of FASM are failed to run as well, but my CPU should support AVX according to Intel website (Core i5-2430M). I tried to run example on Windows 7 (64 bit). I’ve deleted conditional jump and then received windows error message.
Post 15 Mar 2020, 17:14
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donn



Joined: 05 Mar 2010
Posts: 196
donn
Hi, I believe Core i5-2430M is AVX (1). AVX2 and AVX-512 are different and further extend the instruction sets and sizes.

Link:
https://flatassembler.net/docs.php?article=manual#2.1.24
https://ark.intel.com/content/www/us/en/ark/products/53450/intel-core-i5-2430m-processor-3m-cache-up-to-3-00-ghz.html
https://flatassembler.net/docs.php?article=manual#2.1.21
https://software.intel.com/en-us/articles/intel-sdm
https://developer.amd.com/resources/developer-guides-manuals/

The good news is you have more instructions over just SSE instruction sets (more math operations) and you can access wider registers with ymm registers (same as xmm but just more bits each). SSE has had many iterations of improving and maturing its instruction set. You can trace what was added by looking at the changes from MMX through SSE, to AVX-512. Doc links above. I remember trying to compute the dot (scalar) product dppd once on an SSE processor but after looking in these docs, I think it was introduced in SSE 4.1 or something when I only had SSE 4.a. There's a little table in the AMD instruction docs that shows support called Instruction Support.
Post 15 Mar 2020, 19:08
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