Fasm 1.73 Many cmp one jz.

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Roman

Joined: 21 Apr 2012
Posts: 1847

Roman 10 Mar 2020, 05:08

Some time need do many compares. How do many cmps and one jz ?

Code:

    mov    eax,4
    cmp    eax,5
    cmp    eax,3
    cmp    eax,11
    cmp    eax,13
    cmp    eax,23
    cmp    eax,4    ;z=1
    cmp    eax,1    ;reset z = 0 !
    jz        @f
    Msg 'ok'            ;= invoke MessageBox,0,'ok',0,0
@@:

10 Mar 2020, 05:08

ProMiNick

Joined: 24 Mar 2012
Posts: 804
Location: Russian Federation, Sochi

ProMiNick 10 Mar 2020, 05:53

cmp eax,23
ja notinTbl
jmp [eax*4+JmpTbl]
JmpTbl:
dd case0
dd case1
dd case2
dd case3
dd case4
dd case5
dd case6
dd case7
dd case8
dd case9
dd case10
dd case11
dd case12
dd case13
dd case14
dd case15
dd case16
dd case17
dd case18
dd case19
dd case20
dd case21
dd case22
dd case23
case1: case3: case4: case5: case11: case13: case23: Msg 'OK'
notinTbl:
other cases somewhere else (they equal notinTbl forexample)

10 Mar 2020, 05:53

Roman

Joined: 21 Apr 2012
Posts: 1847

Roman 10 Mar 2020, 06:23

Thanks.
I thinked exist simple asm command for my case.
Many times I see that there are not enough many useful commands in modern CPU.
If modern CPU have many simples and powerfuls asm commands. Many peoples writes program on fasm.
And not used c++.

My opinion Intel not good implemented asm commands for easy write code.
This led to the emergence of c ++

Intel should be ashamed for this Smile

10 Mar 2020, 06:23

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 10 Mar 2020, 06:41

Roman wrote:

Thanks.
I thinked exist simple asm command for my case.
Many times I see that there are not enough many useful commands in modern CPU.
If modern CPU have many simples and powerfuls asm commands. Many peoples writes program on fasm.
And not used c++.

My opinion Intel not good implemented asm commands for easy write code.
This led to the emergence of c ++

Intel should be ashamed for this

There certainly some things to shame Intel for, but this isn't one of them IMO. If you think x86 assembly is bad then ALL of the others are also bad, and many are worse, in this respect. I guess some things just don't make sense to do at the low level. The cost/benefit ratio probably doesn't work out well.

10 Mar 2020, 06:41

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8359
Location: Kraków, Poland

Tomasz Grysztar 10 Mar 2020, 07:24

If this is a simple yes/no check with multiple numbers for each case, you could save space by using a bit field and BT instruction:

Code:

        mov     eax,4
        cmp     eax,32
        jae     ok
        bt      [bits],eax
        jc      @f
     ok:
        invoke MessageBox,0,'ok',0,0
     @@:

Code:

bits:
dd   1 shl 3 \
  or 1 shl 4 \
  or 1 shl 5 \
  or 1 shl 11 \
  or 1 shl 13 \
  or 1 shl 23

Note that BT does not need to be limited to 32 cases, you can extend the field if needed:

Code:

        mov     eax,111
        cmp     eax,256
        jae     ok
        bt      [bits],eax
        jc      @f
     ok:
        invoke MessageBox,0,'ok',0,0
     @@:

Code:

bits:
emit 256/8:   1 shl 3 \
           or 1 shl 4 \
           or 1 shl 5 \
           or 1 shl 11 \
           or 1 shl 13 \
           or 1 shl 23 \
           or 1 shl 111

(Here I used fasmg syntax.)

10 Mar 2020, 07:24

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 10 Mar 2020, 12:35

Roman wrote:

Some time need do many compares. How do many cmps and one jz ?

Code:

    mov    eax,4
    cmp    eax,5
    cmp    eax,3
    cmp    eax,11
    cmp    eax,13
    cmp    eax,23
    cmp    eax,4    ;z=1
    cmp    eax,1    ;reset z = 0 !
    jz        @f
    Msg 'ok'            ;= invoke MessageBox,0,'ok',0,0
@@:

In ARM32 code you can use the bitmap trick Tomasz suggested, or make use of the conditional CMP:

Code:

        mov     r0,4
        cmp     r0,5
        cmpne   r0,3
        cmpne   r0,11
        cmpne   r0,13
        cmpne   r0,23
        cmpne   r0,4
        cmpne   r0,1
        beq      @f
        Msg     'ok'
@@:

The first CMP to match the value will disable the remaining CMPs

10 Mar 2020, 12:35

Roman

Joined: 21 Apr 2012
Posts: 1847

Roman 10 Mar 2020, 15:07

Its good example how arm architecture more thoughtful.
Why Intel do not develop new asm commands and do not speed up x86 CPU ?

Efective asm commands give less code and increase speed.

10 Mar 2020, 15:07

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 10 Mar 2020, 16:15

Roman wrote:

Efective asm commands give less code and increase speed.

ARM is targeted to a different market segment so you can't really compare. But in general the performance of ARM is lower than x86. So perhaps all that extra circuitry to support CMPcc is too much of a burden and holds it back?

10 Mar 2020, 16:15

Roman

Joined: 21 Apr 2012
Posts: 1847

Roman 10 Mar 2020, 17:11

Quote:

So perhaps all that extra circuitry to support CMPcc is too much of a burden and holds it back?

This question should be asked to engineers , who develops modern CPU.
And how do this more efective.

10 Mar 2020, 17:11

Roman

Joined: 21 Apr 2012
Posts: 1847

Roman 10 Mar 2020, 17:37

Good example inverse matrix 4x4 ! Nice have one sse asm command.
Inverse matrix 4x4 174 asm sse commands !

It's hard to write 174 asm commands and do not make mystake !

Or one sse command two matrix4x4 multiply. Or cross product.
Quaternion very handfull in math and physics.

But Intel not do this in new AVX instructions.

I think this is probably one of the many reasons why Intel it loses to AMD Ryzen.
No new efective instruction and does not develop new CPU architectures.

10 Mar 2020, 17:37

DimonSoft

Joined: 03 Mar 2010
Posts: 1228
Location: Belarus

DimonSoft 11 Mar 2020, 07:00

Roman wrote:

Its good example how arm architecture more thoughtful.
Why Intel do not develop new asm commands and do not speed up x86 CPU ?

Efective asm commands give less code and increase speed.

You would cry seeing how certain easy things (like, say, loading a 32-bit immediate) are done in ARM.

11 Mar 2020, 07:00

DimonSoft

Joined: 03 Mar 2010
Posts: 1228
Location: Belarus

DimonSoft 11 Mar 2020, 07:06

Roman wrote:

Good example inverse matrix 4x4 ! Nice have one sse asm command.
Inverse matrix 4x4 174 asm sse commands !

It's hard to write 174 asm commands and do not make mystake !

Or one sse command two matrix4x4 multiply. Or cross product.
Quaternion very handfull in math and physics.

But Intel not do this in new AVX instructions.

I think this is probably one of the many reasons why Intel it loses to AMD Ryzen.
No new efective instruction and does not develop new CPU architectures.

What would the inverse matrix instruction do with a zero-determinant matrix?

Does AMD Ryzen have such instructions or you’re just trying to use your personal preferences to explain something unrelated? Think about it.

11 Mar 2020, 07:06

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 11 Mar 2020, 07:27

A "good" example where ARM vs x86 and ARM loses is getting the parity of a number. x86 has a handy flag giving you the parity, ARM has no equivalent, you have to do it longhand.

For most applications this makes no difference, since very few care about the parity. But if your app does make heavy use of parity then you will love x86 and hate ARM.

11 Mar 2020, 07:27

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8359
Location: Kraków, Poland

Tomasz Grysztar 11 Mar 2020, 08:12

revolution wrote:

A "good" example where ARM vs x86 and ARM loses is getting the parity of a number. x86 has a handy flag giving you the parity, ARM has no equivalent, you have to do it longhand.

I feel that this phrasing might be a bit misleading, because "parity of a number" usually means whether the number is even or odd, while x86 parity flag is something different (it is the parity of the sum of 8 bits).

11 Mar 2020, 08:12

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 11 Mar 2020, 09:01

Thanks. I meant the sum of all bits modulo 2. Comms and protocol documents tend to use this definition of parity.

Indeed, the parity in the mathematical sense would simply be the LSb, which is trivial to get in both x86 and ARM.

11 Mar 2020, 09:01

guignol

Joined: 06 Dec 2008
Posts: 763

guignol 18 Apr 2020, 11:47

I was nearly shocked...

and what do you think of
https://amperecomputing.com/ampere-altra-industrys-first-80-core-server-processor-unveiled/

18 Apr 2020, 11:47

Overclick

Joined: 11 Jul 2020
Posts: 669
Location: Ukraine

Overclick 23 Jul 2020, 07:57

Use this macro

Code:

macro cmp arg1, [arg2] {
     common
     counter = 0
     forward
     counter = counter + 1
     common
     if counter > 1
         push           eax
         xor            eax,eax
     forward
         cmp            arg1,arg2
         lahf
         or             al,ah
     common
         mov            ah,al
         sahf
         pop            eax
     else
         cmp            arg1,arg2
     end if
}

Examples:
     cmp      eax,13           ;compiled as usual nothing extra in code
     je       @F
     cmp      eax,13,11,56,44  ;compiled as flags stacker
     je       @F

23 Jul 2020, 07:57

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 23 Jul 2020, 10:24

Overclick wrote:

Use this macro ...

You need to take care that arg1 and arg2 are not rax, eax, ax, ah, or al.

So your example "cmp eax,13,11,56,44" will likely fail.

23 Jul 2020, 10:24

Overclick

Joined: 11 Jul 2020
Posts: 669
Location: Ukraine

Overclick 23 Jul 2020, 14:14

Fixed

For 32 bit version it needs to change registers to eax esp

Code:

macro cmp arg1, [arg2] {
     counter = 0
     forward
     counter = counter + 1
     common
     if counter > 1
         push           rax
         xor            rax,rax
         push           rax
     forward
         mov            rax,[rsp+8]
         cmp            arg1,arg2
         lahf
         or             [rsp],ah
     common
         pop            rax
         mov            ah,al
         sahf
         pop            rax
     else
         cmp            arg1,arg2
     end if
}

Even better if eax not in use

Code:

macro cmp arg1, [arg2] {
     counter = 0
     forward
     counter = counter + 1
     common
     if counter > 1
         push           rax
         xor            rax,rax
         push           rax
      forward
        if `arg1 in <'rax','eax','ax','ah','al'> | `arg2 in <'rax','eax','ax','ah','al'>
         mov            rax,[rsp+8]
        end if
         cmp            arg1,arg2
         lahf
         or             [rsp],ah
      common
         pop            rax
         mov            ah,al
         sahf
         pop            rax
     else
         cmp            arg1,arg2
     end if
}

23 Jul 2020, 14:14

bitRAKE

Joined: 21 Jul 2003
Posts: 4073
Location: vpcmpistri

bitRAKE 23 Jul 2020, 15:44

<OFF TOPIC> fasmg

Code:

macro compare reg0,N&
        iterate n,N
                cmp reg0,n
                if %% > 1
                        pushfq
                        if % = %%
                                repeat %% - 1
                                        pop reg0
                                        or [rsp],reg0
                                end repeat
                                popfq
                        end if
                end if
        end iterate
end macro

compare r15, 0xFF0000,0xFF00,0xFF

only trashes the destination register and flags. extra IF/ENDIF to cover single value use. defining variant names for non-64bit registers would allow macro to be used more generally.

for byte/word size set tests the SIMD string instructions are very effective: PCMP?STR?. the implicit memory forms are not that slow - requires SSE4.2 though.

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23 Jul 2020, 15:44

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