This version adds several new instruction set extensions: AVX512_BITALG, AVX512_VPOPCNTDQ, AVX512_VBMI2, AVX512_VNNI, AVX512_4VNNIW, CET_SS and CET_IBT.

One thing of note is that AVX512_4VNNIW instructions introduce a new syntax variant that looks like: This refers to the fact that the first source operand of this instruction is in fact a block of 4 registers. It is an aligned block (starting with a register that has a number divisible by 4) that contains the specified register. I have made this to not be very strict, the register you specify does not need to be the first register of the block (that is: it does not need to have a number divisible by 4) - so the three other registers may end up being selected on either side of the specified one. The "+3" syntax is also completely optional, you can just use a single register name as the first source operand for the same result.

Please check CMPXCHG and XADD (doesn´t work).
Thanks!

Oh, thank you. I was so focused on testing the new instructions that I forgot to check these two, while I introduced a small "thinko" there. Quickly corrected by 1.73.20.