1.73.08 AVX-512 {sae} bug

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Vic3Dexe

Joined: 16 Feb 2019
Posts: 5

Vic3Dexe 17 Feb 2019, 12:01

Suppose we have instruction with SAE but without rounding:

Code:

vminpd zmm1,zmm2,zmm3,{sae}

Fasm result:

Code:

62 F1 ED 18 5D CB

Lets look at LL' bits (byte 18h), they are = 00, so this is really

Code:

vminpd xmm1,xmm2,xmm3,{sae}  ;??? SAE is applied only to FP-512

But according to Intel SDM (table 2-36 at 2.6.10), for "FP Instructions w/o rounding semantic, can cause #XF" bit B means "SAE" and do not convert LL' to RC.

Am I missing smth?

17 Feb 2019, 12:01

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8357
Location: Kraków, Poland

Tomasz Grysztar 17 Feb 2019, 16:42

Yes, you're right! Thank you! I must have had misinterpreted preliminary documentation back in the day.

I immediately fixed the bug in the AVX-512 macros for fasmg, but I'm afraid fixing it in fasm 1 may take a little longer.

17 Feb 2019, 16:42

Vic3Dexe

Joined: 16 Feb 2019
Posts: 5

Vic3Dexe 17 Feb 2019, 17:03

Tomasz Grysztar wrote:

fixing it in fasm 1 may take a little longer.

No problem! Glad to be helpful.

17 Feb 2019, 17:03

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8357
Location: Kraków, Poland

Tomasz Grysztar 17 Feb 2019, 17:41

Turns out fasm 1 required only a few instructions to fix it. Please test 1.73.09 and let me know if it works correctly.

17 Feb 2019, 17:41

Vic3Dexe

Joined: 16 Feb 2019
Posts: 5

Vic3Dexe 17 Feb 2019, 22:44

Works perfectly. Thx!

17 Feb 2019, 22:44

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