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ProMiNick



Joined: 24 Mar 2012
Posts: 558
Location: Russian Federation, Sochi
ProMiNick
Hello forum members. What fields do you recomend for defining different cpu, to make valid data definition directives, to realize instruction set relative to different cpu specific states.

It is clear that such constants will be defined in preprocessor state via equ or define. (equ preferably)

for structure definitions we need cpu wordsize for instructure alignments and members sizing and we should define them throw architecture independent directives like dbx and never via dependent ones.
For data definition directives we need cpu wordsize (except intel x86 family) that uses historical wordsize instead of actual one.

For everithing except strings we need endianess (it could be separated from cpu at all, because it is relative to particular file formats independent from cpu).

We need field arity to separate binary cpu from not binary ones (for ex. ternary), second needed virtualization of definitions, and completely different set of data definition macros.
We need byte (memory atom) size to determine is virtualization of definitions needed or not.
For instruction set we need instruction size (41 bit for IA64, 32 bit for ARM, variable for x86 etc.), if it not module of 8 we again needed virtualization for realizing binary flow of instruction definitions.

For each cpu we need set of states specific only for that cpu (cpu family) to detemine form and allowence of instructions.

So, flags are:
cpuArity equ ;2,3 etc; and its syninim cpuAtomSize
cpuFamily ; include includes relative to cpu family
cpuInstrSetDefs ; include includes relative to cpus with common instruction set
cpuInstrSubset ; type(s) of cpu supported only instruction subset
cpuWordsize ;for in structure alignments and member sizes
cpuHistoricalWordsize ;i86 override for cpuWordsize only for case of data definition macros (maybe that set should be defined in cpuFamily relative includes)
cpuMemAtomSize ; 8 for 8 bit byte, that don`t needed in virtualization of definitions
cpuMemAtomAlignedInstructions ; if yes that don`t needed in virtualization of definition instructions
cpuInstructionSize ; internaly by instruction handling used (unused via core or used if set realized via macros)
cpuType ; Type is set of cpu that holds same set of modes: 16,32,64 (intermixed with REAL,UNREAL,VIRTUAL,PROTECTED,LONG and RINGS) or ARM, THUMB, etc.
cpuTypemode; array of 64 bit sets cpuTypemode1,cpuTypemode2 etc. if needed to cover all modes variants.
Endianess

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Post 29 Oct 2018, 10:20
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17463
Location: In your JS exploiting you and your system
revolution
IMO simply having a setting to enable or disable each class of instruction set is the best approach. So similar to the format used by fasmarm just have each class controlled by a single setting. That way users can construct the instruction sets for their target CPUs exactly as it is supported, without having to figure out which family and which type etc., and then apply patches to account for individual variants and whatnot for each particular CPU.

If you do like your post above then there are so many variants within each family/type/etc and the flags and settings tend to become very confusing. IMO of course.
Post 29 Oct 2018, 10:35
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ProMiNick



Joined: 24 Mar 2012
Posts: 558
Location: Russian Federation, Sochi
ProMiNick
revolution, Thou touch only one aspect "instruction subset".
But what if I going to realize couple of ternary subsets? with not only different instruction sets, but with different wordsize,mematomsize, InstructionSize & Typemodes.
For both of them I can create architecture independent ternary variant of data definition "dtx" that defines 18 bit (9 for + trit,9 for - trit) in output, but followed with org increasing address by 1 (tryte), and that is for every tryte. And use it in all ternary subsets.

And what if I going to add endianess? so with all data definitions (except db & du) I should override them with variants that split value on byte sequence & change their order, such changes are common for all rest data definitions of all cpu.

I hhink each above flag can wrap code in higher abstraction level, than each instruction set would be just realized in raw format (without any relation to other formats).
Post 29 Oct 2018, 11:47
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ProMiNick



Joined: 24 Mar 2012
Posts: 558
Location: Russian Federation, Sochi
ProMiNick
for ternary dt is like db for binary
Code:
macro splitternary _pos,_neg,size,val {
        local tval,s,d
        s    = 0
        _neg = 0
        _pos = 0
        if val<0
                s=3
                tval = -val
        else
                tval  = val
        end if
        size = 27
        repeat 27
                if ~tval
                        size = (%+9)/9
                d = (tval mod 3) xor s
                _pos = _pos + (d and 1) shl %
                _neg = _neg + (d and 2) shl %
                tval = tval / 3
        end repeat
}

$_bit = 0;,2,4,6
virtual at 0
ternary::
;end virtual

macro dt val {
        end virtual
        if ~$_bit
                db             + (_pos0 shl 0) and $FF,\
                   _pos0 shr 8 + (_neg0 shl 1) and $FE,\
                   _neg0 shr 7 + (_pos2 shl 2) and $FC,\
                   _pos2 shr 6 + (_neg2 shl 3) and $F8,\
                   _neg2 shr 5 + (_pos4 shl 4) and $F0,\
                   _pos4 shr 4 + (_neg4 shl 5) and $C0,\
                   _neg4 shr 3 + (_pos6 shl 6) and $80,\
                   _pos6 shr 2 + (_neg6 shl 7) and $FF,\
                   _neg6 shr 1
                _pos0 = 0
                _neg0 = 0
                _pos2 = 0
                _neg2 = 0
                _pos4 = 0
                _neg4 = 0
                _pos6 = 0
                _neg6 = 0
        end if
        splitternary _pos#$_bit,_neg#$_bit,sizeof.#val,val
        $_bit = ($_bit + 2) and 7;and 6 no matter
        virtual ternary
        db $_bit
}

macro dt [val] {
        local $"
        label $"
        match =?,val {dt 0 \}
        match count =dup(=?),val {
                repeat count
                        dt 0
                end repeat\}
        if $=$"
                dt val
        end if
}    
Post 29 Oct 2018, 21:07
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17463
Location: In your JS exploiting you and your system
revolution
I think that instruction size and data size combinations can also use enable/disable settings. Even if the CPU supports multiple sizes, there is still the notion of CPU execution modes that will limit which set is active at any particular time. For example: at start-up the x86 CPUs can only execute 16-bit code and data encodings even though the CPU is capable of full 32-bit and 64-bit in different modes. And later when the CPU is in long mode all 16-bit code shouldn't be accessible accidentally by the programmer.
Post 30 Oct 2018, 19:15
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ProMiNick



Joined: 24 Mar 2012
Posts: 558
Location: Russian Federation, Sochi
ProMiNick
Absolutely agree.
That one of things I would like to see in boot codes:
When cpu switched mode with instruction, manualy show to programmer by some directive(directive or macro no matter on what level of language) that allowed instruction set(and/or data size) is changed.
Boot structures members have order, position & sizes independent from cpu mode switches .

Instruction that generate exception in ubnormal way shouldn`t be allowed in programs for ring3, programmer should with directive up ring level (or change mode to real or whatever), and than he can place such instruction, than he can return mode (if needed to place 1 specific instruction only). At that point there are maximal clearance that mode will not changed just by directive, so it generates exceptions. Same way could be protected not obly instructions, but memory ranges too from accidentaly accessing.
Post 30 Oct 2018, 20:09
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