endianess support added but it too pure (just BE & LE without mixing stages)
macro dbx statement& {
local size
match sz:args,statement {
if sz eqtype byte
size = sizeof.\#sz
else
size = sz
end if
assert size<9 & size>-1
irp arg,args {
if arg shr (8*size)
db arg
else
repeat size
if defined __cpu"ENDIANESS" & __cpu"ENDIANESS"<>__cpu"ENDIANESS"LE
db arg shr (8*(size-%)) and $FF
else
db arg shr (8*(%-1)) and $FF
end if
end repeat
end if
\\}
\}
}
__cpu"ENDIANESS"LE = 0
__cpu"ENDIANESS"BE = 1
__cpu"ENDIANESS"LEW = 2 ; size of word different from cpu to cpu, word endianess reversed
__cpu"ENDIANESS"BEW = 3
sizeof.byte = 1
dbx byte:$FF,$34
__cpu"ENDIANESS" = __cpu"ENDIANESS"LE
dbx 7:$13,$55
__cpu"ENDIANESS" = __cpu"ENDIANESS"BE
dbx 7:$27,$14
output is
FF 34 13 00 00 00 00 00
00 55 00 00 00 00 00 00
00 00 00 00 00 00 27 00
00 00 00 00 00 14
works on both fasm1x (original & arm)