Hello, i have just one question, how is it possible in assembly to use multiprocessoring ? Have you got simple example ?

Depends on what you mean by “multiprocessoring”, i.e. what particular task you’re trying to solve.

If you are using an existing OS then you can use the threading APIs to get other threads running.

Then there are the synchronisation APIs you can use to get things happening in the sequence you need.

No, its about os construction.

For example, i would like to use first core or my processor to launch 16bits code, and use second to launch 64bits code.

Is it possible ?

Moved to "OS Construction"

This topic may help: https://board.flatassembler.net/topic.php?p=108312

You have to send inter-processor interrupts (IPI) to the other cores, which requires that interrupts are properly set up for IO APIC, which in turn requires either the multi-processor (MP) table information from BIOS or (if I remember correctly) the later x2APIC and ACPI tables.

I have looked your example, but i don't understand very well.

How you can, for example launch in parralel 32 bits and 16 code at the same time. Is it in real time ? Or multiprocess is impossible ?

I have studied the problem.

I need i think to make TSS descriptor into GDT and enable multiprocessoring.

Do you know good documentation about multiprocessoring ?

yep, intel architecture manual
https://software.intel.com/en-us/articles/intel-sdm

TSS is related to task switching, and isn't directly related to using multiple CPUs.

If you want to use multiple processors (either logical or physical CPUs) then you will need to look into communicating between your CPUs. Read about the mailbox for passing messages among the processors in the system.

if you have UEFI there are multiprocessor protocols so you can do some experiments even without OS
here you have a sample
https://board.flatassembler.net/topic.php?t=16187
the sample tries 3 ways: the most common MP protocol, if it fails then second one, if both fail then manually (sending INIT-SIPI) - the manual way is just as simple as possible as it does not care about possible defective cores turned off by firmware (it sends IPI from BSP to all but self so it can wake up defective cores)

there is also one tricky way if you want to use only BIOS and your code is realmode - hooking int2 vector, sending NMI to all but self so AP CPUs start to execute code from NMI vector = int2 and then restore the NMI vector (this is possible because firmware already woke up every CPU when enumerating them while creating ACPI tables and then put them asleep state from which they could be waken up by NMI) but anyway in this case the BSP CPU must enable protected mode and paging to be able to reach APIC (memory at physical address FEE00000h) to send the IPI, you also have to solve a stack problem as all CPUs start with the same SS:SP at the same time (e.g. using CPUID to get APIC ID which is unique so you can setup unique stack for every CPU)

tell us revō what does differ thread from a core
like about that one 64-core CPU with 128 threads
?