flat assembler
Message board for the users of flat assembler.
Index
> Non-x86 architectures > how different are non x86 assemblers/cpus? |
Author |
|
alexfru 14 May 2018, 10:33
Traditional ARM and MIPS have 4-byte-long instructions and can be big- or little-endian.
They are load-store CPUs, that is, there are no memory to memory move/add/etc instructions. They are very regular/orthogonal CPUs, having very few registers or instructions that are hardwired together (like x86 xlat with bx and al, loop with cx, (i)div with ax and dx, etc). Both have many 32-bit general-purpose registers (16 in ARM, 32 in MIPS). ARM has flags. MIPS doesn't. ARM supports branchless conditional execution of instructions. MIPS doesn't. Originally both required naturally aligned memory operands. MIPS memory operands are of the form: register+offset. ARM also has reg1+reg2*scale, AFAIR. ARM has PC-relative addressing. MIPS doesn't. ARM may have no divider on chip. MIPS branches have delay slots. Etc. Modern ARM and MIPS processors are more interesting and powerful. There're more compact ISAs (e.g. Thumb, Thumb2, MIPS16e, microMIPS, nanoMIPS). And 64-bit as well. Buy the i8051 if you wan to know everything down to a single transistor. Reportedly, the smallest implementation has 2700 gates. The i8086 had some 20000+. MIPS32 - 1 to 5 million as far as I can see. Modern stuff is hopelessly large and complex for a single person to understand fully in any reasonable amount of time. Here's one compiled table: A History of Microprocessor Transistor Count 1971 to 2013. I could also write a bit about i8051, i8080/Z80, TMS320C54xx. But really, if you get the right doc/datasheet, you can see most of stuff yourself. There's usually enough overview and tables/diagrams to give you an idea of how things are the same as or different from what you already know. |
|||
14 May 2018, 10:33 |
|
DimonSoft 14 May 2018, 10:50
Raymond has a few series on non-x86 architectures.
Alpha AXP: The Alpha AXP, part 1: Initial plunge The Alpha AXP, part 2: Integer calculations The Alpha AXP, part 3: Integer constants The Alpha AXP, part 4: Bit 15. Ugh. Bit 15. The Alpha AXP, part 5: Conditional operations and control flow The Alpha AXP, part 6: Memory access, basics The Alpha AXP, part 7: Memory access, loading unaligned data The Alpha AXP, part 8: Memory access, storing bytes and words and unaligned data The Alpha AXP, part 9: The memory model and atomic memory operations The Alpha AXP, part 10: Atomic updates to byte and word memory units The Alpha AXP, part 11: Processor faults The Alpha AXP: Part 12: How you detect carry on a processor with no carry? The Alpha AXP, part 13: On treating a 64-bit processor as if it were a 32-bit processor The Alpha AXP, part 14: On the strange behavior of writes to the zero register The Alpha AXP, part 15: Variadic functions The Alpha AXP, part 16: What are the dire consequences of having 32-bit values in non-canonical form? The Alpha AXP, part 17: Reconstructing a call stack MIPS R4000: The MIPS R4000, part 1: Introduction The MIPS R4000, part 2: 32-bit integer calculations The MIPS R4000, part 3: Multiplication, division, and the temperamental HI and LO registers The MIPS R4000, part 4: Constants The MIPS R4000, part 5: Memory access (aligned) The MIPS R4000, part 6: Memory access (unaligned) The MIPS R4000, part 7: Memory access (atomic) The MIPS R4000, part 8: Control transfer The MIPS R4000, part 9: Stupid branch delay slot tricks The MIPS R4000, part 10: Trampolines and stubs The MIPS R4000, part 11: More on branch delay slots The MIPS R4000, part 12: Calling convention The MIPS R4000, part 13: Function prologues and epilogues The MIPS R4000, part 14: Common patterns The MIPS R4000, part 15: Code walkthrough UPD 17.08.2018 PowerPC: The PowerPC 600 series, part 1: Introduction The PowerPC 600 series, part 2: Condition registers and the integer exception register The PowerPC 600 series, part 3: Arithmetic The PowerPC 600 series, part 4: Bitwise operations and constants The PowerPC 600 series, part 5: Rotates and shifts The PowerPC 600 series, part 6: Memory access The PowerPC 600 series, part 7: Atomic memory access and cache coherency The PowerPC 600 series, part 8: Control transfer The PowerPC 600 series, part 9: The table of contents The PowerPC 600 series, part 10: Passing parameters, function prologues and epilogues The PowerPC 600 series, part 11: Glue routines The PowerPC 600 series, part 12: Leaf functions The PowerPC 600 series, part 13: Common patterns The PowerPC 600 series, part 14: Code walkthrough Last edited by DimonSoft on 31 Oct 2018, 07:43; edited 2 times in total |
|||
14 May 2018, 10:50 |
|
bitRAKE 14 May 2018, 21:31
68000 was the first assembly language I programmed. Many similarities between x86 and 68k. Both are CISC, encodings are various lengths. I miss the MOVEM instruction - multiple registers can be moved at once to/from memory - it's like a universal adapter for calling conventions. TRAP instruction is like INT. Memory operations can automatically advance the pointer - which made for rather tight loops.
http://68k.hax.com/ It's been over 20 years since I've played with it, but the demo scene for 68k is still quite active. Some chips will never die it seems: Z80, 6502, 68k, x86, ... _________________ ¯\(°_o)/¯ “languages are not safe - uses can be” Bjarne Stroustrup |
|||
14 May 2018, 21:31 |
|
rugxulo 15 May 2018, 00:58
Try learning Knuth's MMIX.
|
|||
15 May 2018, 00:58 |
|
rugxulo 15 May 2018, 21:09
Also take a look at SuperH, which seems to be having a resurgence (soon?).
|
|||
15 May 2018, 21:09 |
|
< Last Thread | Next Thread > |
Forum Rules:
|
Copyright © 1999-2025, Tomasz Grysztar. Also on GitHub, YouTube.
Website powered by rwasa.