I found this article by randomly googling "thread stack address".

https://software.intel.com/en-us/articles/adjusting-thread-stack-address-to-improve-performance-on-intel-xeonr-processors

I don't get it. They recommend wasting space on stack for some reason, in multithreaded apps? I haven't heard anything like that before. Is this real?

"Two threads with very similar stack frame images and access patterns to local variables on the stack are very likely to cause alias conflicts resulting in significant performance degradation."

Maybe this one:
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
3.6.7 Stack Alignment

At some point it talks about the stalls happening when code mixes store/loads with addresses, which are different by a MULTIPLE of 4Kb. Usually stack frames are different by these values.

Probably their concern is with caching. The number of sets/ways of the cache subsystem can cause aliasing problems (i.e. thrashing) when you have accesses that align in multiples of the cache geometry. Note that the cache thrashing can apply to one or both of 1) the "normal" memory cache, and 2) the TLB cache.

The first link mentions counting "the number of 64KB alias events". Is it possible to actually receive and count them? How?