flat assembler
Message board for the users of flat assembler.

Index > Main > 32-bit value when concatenating two dwords

Author
Thread Post new topic Reply to topic
zhong



Joined: 12 Jan 2017
Posts: 24
Location: youxi, jiangjin, chongqing, china.
zhong 05 Mar 2017, 10:37
thread:
mov r8d,'my n'
mov r9d,'li m'
xor r10,r10
add r10d,r8d
shl r10,20h
add r10d,r9d;ce 6.6 debug error.
ret

Edit by revolution: Changed title to reflect the actual problem

_________________
zhengxing zhong.
Post 05 Mar 2017, 10:37
View user's profile Send private message Send e-mail Reply with quote
revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 20454
Location: In your JS exploiting you and your system
revolution 05 Mar 2017, 10:45
Assembles fine for me.
Code:
use64
thread:
mov r8d,'my n'
mov r9d,'li m'
xor r10,r10
add r10d,r8d
shl r10,20h
add r10d,r9d;ce 6.6 debug error.
ret    
Is there anything in particular you have found wrong?

Perhaps you can post a minimal example that shows the error?
Post 05 Mar 2017, 10:45
View user's profile Send private message Visit poster's website Reply with quote
zhong



Joined: 12 Jan 2017
Posts: 24
Location: youxi, jiangjin, chongqing, china.
zhong 05 Mar 2017, 10:51
add r10d,r9d;ce 6.6 debug error.
this is the key, if you use cheat engine create process to debug, the r10 will never become 'my nli m', but instead, become 'li m'.
Post 05 Mar 2017, 10:51
View user's profile Send private message Send e-mail Reply with quote
revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 20454
Location: In your JS exploiting you and your system
revolution 05 Mar 2017, 11:10
You are using the 32-bit register r10d. If you need a 64-bit value then you need to use the full register r10.
Code:
use64
thread:
mov r8d,'my n'
mov r9d,'li m'
xor r10,r10
add r10d,r8d
shl r10,20h
or r10,r9  ;<--- use a 64-bit register here
ret    
Post 05 Mar 2017, 11:10
View user's profile Send private message Visit poster's website Reply with quote
zhong



Joined: 12 Jan 2017
Posts: 24
Location: youxi, jiangjin, chongqing, china.
zhong 05 Mar 2017, 11:33
thread:
mov al,'m'
mov bl,'l'
xor cx,cx
add cl,al
shl cx,8h
add cl,bl
ret

this time i have to use dosbox and tasm's td, smile.
Post 05 Mar 2017, 11:33
View user's profile Send private message Send e-mail Reply with quote
revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 20454
Location: In your JS exploiting you and your system
revolution 05 Mar 2017, 11:44
In x86-64 CPUs: When you use a 32-bit register as a destination from any operation the upper 32-bit are zeroed. This is the design of the hardware. It is not a bug in the assembler. And it is not a bug in the CPU. It is by design.
Post 05 Mar 2017, 11:44
View user's profile Send private message Visit poster's website Reply with quote
zhong



Joined: 12 Jan 2017
Posts: 24
Location: youxi, jiangjin, chongqing, china.
zhong 05 Mar 2017, 11:51
thanks, i just transform my qb64 thread into fasm thread.
Post 05 Mar 2017, 11:51
View user's profile Send private message Send e-mail Reply with quote
Display posts from previous:
Post new topic Reply to topic

Jump to:  


< Last Thread | Next Thread >
Forum Rules:
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
You cannot attach files in this forum
You can download files in this forum


Copyright © 1999-2025, Tomasz Grysztar. Also on GitHub, YouTube.

Website powered by rwasa.