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Index > Main > MOVZX AX, BX

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l4m2



Joined: 15 Jan 2015
Posts: 674
l4m2 06 Jan 2017, 04:34
In fasm MOVZX AX,BX compiles error but
In c32asm can get (16B)
Code:
0FB7C3 MOVZX AX, BX
0FBFC3 MOVSX AX, BX
8BC3   MOV   AX, BX
89D8   MOV   AX, BX
    

Do they do the same thing?
Post 06 Jan 2017, 04:34
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Mikl___



Joined: 30 Dec 2014
Posts: 125
Location: Russian Federation, Irkutsk
Mikl___ 06 Jan 2017, 06:43
Code:
660FB7C3 MOVZX AX,BX
0FB7C3   MOVZX EAX,BX
8D03     LEA EAX,[EBX]=MOV EAX,EBX
678D07   LEA EAX,[BX]=MOVZX EAX,BX
660FBFC3 MOVSX AX, BX
0FBFC3   MOVSX EAX,BX    
Post 06 Jan 2017, 06:43
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nop



Joined: 01 Sep 2008
Posts: 165
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nop 06 Jan 2017, 06:46
movzx & movsx only makes sense if 1st operand has more bits than last operand like movzx eax,bx
Post 06 Jan 2017, 06:46
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Mikl___



Joined: 30 Dec 2014
Posts: 125
Location: Russian Federation, Irkutsk
Mikl___ 06 Jan 2017, 06:57
nop,
if you write
Code:
db 66h
movzx eax,bx    
then you will get
Code:
movzx ax,bx    
Post 06 Jan 2017, 06:57
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nop



Joined: 01 Sep 2008
Posts: 165
Location: right here left there
nop 06 Jan 2017, 19:29
but im saying why would you want movzx ax,bx in the first place? why try to zero extend bits that dont exist Rolling Eyes maybe thats why fasm wont accept it
Post 06 Jan 2017, 19:29
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 8250
Location: Kraków, Poland
Tomasz Grysztar 06 Jan 2017, 19:48
Such combination of operands was never listed in Intel manuals, the only ones listed for 32-bit processors were:
Code:
MOVZX r16,r/m8 Move byte to word with zero-extension
MOVZX r32,r/m8 Move byte to doubleword, zero-extension
MOVZX r32,r/m16 Move word to doubleword, zero-extension    
You should be careful with over-interpreting combinations of operands that are not officially defined for instructions, though encodable. For example LDS/LES instructions have only "r,m" combinations defined, though you could theoretically encode "r,r" with the same instruction code. But such combination was never officially defined and years later Intel used the sequences of codes that would correspond to theoretical "LDS r,r" instruction for a very different purpose: these codes are now part of the VEX prefix space for AVX instructions.
Post 06 Jan 2017, 19:48
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nop



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Posts: 165
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nop 06 Jan 2017, 20:03
yes a very wise precaution tomasz Wink
Post 06 Jan 2017, 20:03
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l4m2



Joined: 15 Jan 2015
Posts: 674
l4m2 07 Jan 2017, 02:10
Tomasz Grysztar wrote:

So they behave same now but not later?
p.s. I remember debug.com uses les sp,ax(or anything, i forgot) to have an interrupt?
Post 07 Jan 2017, 02:10
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