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Index > OS Construction > 32-bit addressing in RM

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nkeck72



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nkeck72 28 Sep 2016, 13:39
I was reading up on 32-bit addressing schemes on the OSDev wiki. and I came across this little exciting bit of info:

Quote:
Note that you can still use 32-bit addressing modes in Real Mode, simply by adding the "Address Size Override Prefix" (0x67) to the beginning of any instruction. Your assembler is likely to do this for you, if you simply try to use a 32-bit addressing mode. But you are still constrained by the current "limit" for the segment that you use in each memory access (always 64K in Real Mode -- Unreal Mode can be bigger).


Does this technically mean I can address more than 1MB of RAM, but can only use it in 64k segments, or am I still limited to 640k of conventional RAM, plus the HMA?
[/code]

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Post 28 Sep 2016, 13:39
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revolution
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revolution 28 Sep 2016, 13:42
In RM with standard limit settings in the segment shadow registers you can address up to (1M + 64K - 16) bytes. That is addresses from 0x00000 to (0xFFFF * 16 + 0xFFFF).
Post 28 Sep 2016, 13:42
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nkeck72



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nkeck72 29 Sep 2016, 21:25
So a little over a megabyte with standard settings. But the question remains, what about with the 67h prefix?
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revolution
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revolution 29 Sep 2016, 22:22
nkeck72 wrote:
But the question remains, what about with the 67h prefix?
No change. All it gives you is the addressing modes*. It won't give you more addressing space, it doesn't alter the segment shadow registers.

* Things like "mov dx,[ecx+eax*4]" etc.
Post 29 Sep 2016, 22:22
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nkeck72



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nkeck72 04 Oct 2016, 01:36
Ah, gotcha. thanks.
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neville



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neville 22 Oct 2016, 23:12
What revo didn't mention was that setting the segment limits to 4Gigabytes in real mode makes 32-bit addressing VERY useful. Code still has to be executed in the conventional 20-bit 1M byte address space, but you have direct linear access to the entire 32-bit address space for data and/or relocatable code.

[rant]There is no magic or voodoo about this, as some people like to claim. I call it Linear Memory Mode in my FAMOS os, but it is also known as Big Real Mode or Unreal Mode. It's just a pity that it was too useful and logical for Intel or AMD to replicate it in any of the 64-bit modes. Instead, they opted to insist on Paging in Long Mode, which is even more cumbersome and tedious than Segmentation in the original Real Mode![/rant]

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Post 22 Oct 2016, 23:12
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ivan_tux



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ivan_tux 05 Nov 2016, 00:53
nkeck72 wrote:
Does this technically mean I can address more than 1MB of RAM, but can only use it in 64k segments, or am I still limited to 640k of conventional RAM, plus the HMA?

Maybe yes, After A20 enabled and your os still in RM; you can do this
Code:
mov al,[0x80000000]    

This will point to actual address DS * 0x10 + 0x80000000
But, for stack pointer, instruction pointer and data pointer will always grow automatically in 16-bit way.
So; stosd, stosb, stosb will only increment SI and DI; not ESI and EDI. And, when IP goes to 0xFFFF, it will be back to 0x0000
Post 05 Nov 2016, 00:53
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revolution
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revolution 05 Nov 2016, 00:56
ivan_tux wrote:
nkeck72 wrote:
Does this technically mean I can address more than 1MB of RAM, but can only use it in 64k segments, or am I still limited to 640k of conventional RAM, plus the HMA?

Maybe yes, After A20 enabled and your os still in RM; you can do this
Code:
mov al,[0x80000000]    
This won't work in real mode. Perhaps you are thinking of unreal mode where the shadow segment limits are set to 0xffffffff?
Post 05 Nov 2016, 00:56
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