macro mov op1, op2 {
  if op1 in <cs,ds,es,fs,gs,ss> & op2 in <cs,ds,es,fs,gs,ss>
    push op2
    pop op1
  else if op1 eqtype eax & op2 eqtype eax+eax
    local cax, cbx, ccx, cdx, csi, cdi, cbp, csp, ceax, cebx, cecx, cedx, cesi, cedi, cebp, cesp
    irp reg, ax, bx, cx, dx, si, di, bp, sp, eax, ebx, ecx, edx, esi, edi, ebp, esp \{
      reg equ 0
    \}
    c = op2
    ax equ 1
    cax = op2 - c
    restore ax
    bx equ 1
    cbx = op2 - c    
    restore bx    
    cx equ 1    
    ccx = op2 - c    
    restore cx    
    dx equ 1    
    cdx = op2 - c    
    restore dx    
    si equ 1    
    csi = op2 - c    
    restore si    
    di equ 1    
    cdi = op2 - c    
    restore di    
    bp equ 1    
    cbp = op2 - c    
    restore bp    
    sp equ 1    
    csp = op2 - c    
    restore sp    
    eax equ 1    
    ceax = op2 - c    
    restore eax    
    ebx equ 1    
    cebx = op2 - c    
    restore ebx    
    ecx equ 1    
    cecx = op2 - c    
    restore ecx    
    edx equ 1    
    cedx = op2 - c    
    restore edx    
    esi equ 1    
    cesi = op2 - c    
    restore esi    
    edi equ 1    
    cedi = op2 - c    
    restore edi    
    ebp equ 1    
    cebp = op2 - c    
    restore ebp    
    esp equ 1    
    cesp = op2 - c    
    restore esp    
    q = 0
    irp reg, cax, cbx, ccx, cdx, csi, cdi, cbp, csp \{
      if reg<>0
        q = q or 1
      end if
    \}
    irp reg, ceax, cebx, cecx, cedx, cesi, cedi, cebp, cesp \{
      if reg<>0
        q = q or 2
      end if
    \}
    irp reg, ax, bx, cx, dx, si, di, bp, sp, eax, ebx, ecx, edx, esi, edi, ebp, esp \{
      restore reg
    \}
    if q = 0
      mov op1, op2
    else if q = 1 ;16 bit
      if op1 in <eax, ebx, ecx, edx, esi, edi, ebp, esp>
        err
      end if
      irp reg, cax, ccx, cdx, csp \{
        if reg<>0
          q = q or 4
        end if
      \}
      irp reg, cbx, cbp \{
        if reg<0 | reg>1
          q = q or 4
        end if
        q = q + reg * 16
      \}
      irp reg, csi, cdi \{
        if reg<0 | reg>1
          q = q or 4
        end if
        q = q + reg * 64
      \}
      if q and 164 <> 0
        c equ op1
        ax equ eax
        bx equ ebx
        cx equ ecx
        dx equ edx
        si equ esi
        di equ edi
        bp equ ebp
        sp equ esp
        lea c, [op2]
        irp reg, ax, bx, cx, dx, si, di, bp, sp \{ restore reg \}
      else
        lea op1, [op2]
      end if
    else if q=2 ;32bit
      if op1 in <ax, bx, cx, dx, si, di, bp, sp>
        err
      end if
      lea op1, [op2]
    else
      err
    end if
  else
    mov op1, op2
  end if
}     

macro mov op1, op2 {
  if op1 in <cs,ds,es,fs,gs,ss> & op2 in <cs,ds,es,fs,gs,ss>
    push op2
    pop op1
  else if op1 eqtype eax & op2 eqtype eax+eax
    local c, d, q
    macro catch d, src \{d equ c#src\}
    irp reg, ax, bx, cx, dx, si, di, bp, sp, eax, ebx, ecx, edx, esi, edi, ebp, esp \{
      catch d, reg
      match r, d \\{
        local r
      \\}
      reg equ 0
    \}
    c = op2
    irp reg, ax, bx, cx, dx, si, di, bp, sp, eax, ebx, ecx, edx, esi, edi, ebp, esp \{
      reg equ 1
      catch d, reg
      d = op2 - c
      restore reg
    \}
    q = 0
    irp reg, ax, bx, cx, dx, si, di, bp, sp \{
      catch d, reg
      dispint d
      if d<>0
        q = q or 1
      end if
      dispint d
    \}
    irp reg, eax, ebx, ecx, edx, esi, edi, ebp, esp \{
      catch d, reg
      if d<>0
        q = q or 2
      end if
      dispint d
    \}
    irp reg, ax, bx, cx, dx, si, di, bp, sp, eax, ebx, ecx, edx, esi, edi, ebp, esp \{
      restore reg
    \}
    if q = 0
      mov op1, op2
    else if q = 1 ;16 bit
      if op1 in <eax, ebx, ecx, edx, esi, edi, ebp, esp>
        err
      end if
      irp reg, ax, cx, dx, sp \{
        catch d, reg
        if d<>0
          q = q or 4
        end if
      \}
      irp reg, bx, bp \{
        catch d, reg
        if d<0 | d>1
          q = q or 4
        end if
        q = q + d * 16
      \}
      irp reg, si, di \{
        catch d, reg
        if d<0 | d>1
          q = q or 4
        end if
        q = q + d * 64
      \}
      if q and 164 <> 0
        ax equ eax
        bx equ ebx
        cx equ ecx
        dx equ edx
        si equ esi
        di equ edi
        bp equ ebp
        sp equ esp
        lea op1, [op2]
        irp reg, ax, bx, cx, dx, si, di, bp, sp \{ restore reg \}
      end if
      lea op1, [op2]
    else if q=2 ;32bit
      if op1 in <ax, bx, cx, dx, si, di, bp, sp>
        err
      end if
      lea op1, [op2]
    else
      err
    end if
  else
    mov op1, op2
  end if
}