cs:cs:cs:cs:nop
cs:ss:movsb
66 67 66 67 mov ax,[bx]
66 mov al,5

IIRC last segment register wins.

I don't think has the meaning of "what will happen if an interrupt happens ~"and so on

Nothing unusual. The interrupt is taken and then return to the code to execute the next instruction. You can put as many prefixes as you want with the only limitation being the entire instruction length must be 15 bytes or less.

Usually interrupts will be handled at the end of an instruction only - otherwise you will have unpredicted results. What should happen if an interrupt occurs when reading the first, second, third, fourth byte of an instruction ? The interrupt interrupts the program not the current instruction.

Let's say 66 cs:cs:cs:...cs:mov ax,bx. the 66thrown ?

A single instruction consists of all prefixes and the final opcode and operands, Interrupts cannot occur within an instruction. It just won't happen. Interrupts only occur between instruction boundaries.

All of the code below is considered a single instruction and an interrupt cannot occur within those 15 bytes:

If I remember correctly, no more than 4 prefixes allowed. Pls consult CPU manuals. Also instruction limit is 15 bytes I think (or maybe 16?). And yes, interrupt cannot be fired inside instruction.

It is easy to test: If you change the times parameter to 15 the program will fault.

By the way - block instructions can be interrupted as they are executed as single instructions in a loop which maybe interrupted. On the Z80 interrupts are accepted during all LDIR/LDDR, CPIR/CPDR, OTIR/OTDR instructions. Think this is quite similar to x86 instructions with REP prefix for example - would be interesting to see if all necessary flags are restored like direction flag - would be nice to test.

Logically something like "rep lodsb" is still a single instruction. So it can't be interrupted in the middle of rep and lodsb but it can interrupt at any iteration count. The interrupt function will see the return address pointing to the beginning of rep. Register values for [R|E]SI, [R|E]DI and [R|E]CX are updated before entering the ISR. If the ISR alters DF then [R|E]SI and [R|E]DI will go in the opposite direction from before it was interrupted. If your ISR alters DF then expect bad things to happen. But remember that the ISR can alter all register values anyway so [R|E]SI, [R|E]DI and [R|E]CX could come back with different values also.

Yes you are right - it is the job of the ISR to save the flag register and all used registers ...