I willl be searching soon, just thought you may know of a good one before I search

How do pages get mapped, specifically to the real memory locales?

In running code in paging, do you jump into a page, and run your OS (or ring 0 code) from there?

Is it paged memory, or does the OS continue to run in non-paged environment?

there is a potential problem within the first 2 MB of memory, where there are ROMs, Video RAM buffer, and BIOS, do you still map that 2 MB as continuous memory area

How do you get out of paging, and back to running in a specific physical memory area?

You'll need an idempotent mapping at least for the pages with the code that performs the switching procedure.

I find the semantics a little different from your vernacular

I think Intel uses Linear Addressing as a coin for a virtual memory space, to a physical address

Even within Chapter 3 Intel confuses by interchanging terminology

smiddy

Quote:

I think Intel uses Linear Addressing as a coin for a virtual memory space, to a physical address

This statement doesn't make any sense to me. The term "virtual memory space" doesn't exist. There are "virtual address" (which is out of scope of the Intel's documentation, because it should be defined by the OS), "virtual memory" (which is not a part of a CPU architecture and is only mentioned by Intel as something that can be implemented by an OS using paging) and "address space" (which is just a set of all possible numeric values of an address of whatever kind).

Quote:

Even within Chapter 3 Intel confuses by interchanging terminology

I don't think, they confuse anything. Please provide a couple of statements from the documentation that, as you think, are inconsistent.

Your initial terminology was different

Virtual memory space very much does exist: https://software.intel.com/en-us/articles/recap-virtual-memory-and-cache#Virtual_Memory

BTW, I said they confuse me, not you (that is implied in my sentence)

Why did you take it personal?

3.1 MEMORY MANAGEMENT OVERVIEW
The memory management facilities of the IA-32 architecture are divided into two parts: segmentation and paging.
Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple
programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mechanism
for implementing a conventional demand-paged, virtual-memory system where sections of a program’s
execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation
between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is
no mode bit to disable segmentation. The use of paging, however, is optional.
These two mechanisms (segmentation and paging) can be configured to support simple single-program (or singletask)
systems, multitasking systems, or multiple-processor systems that used shared memory.
As shown in Figure 3-1, segmentation provides a mechanism for dividing the processor’s addressable memory
space (called the linear address space) into smaller protected address spaces called segments. Segments can
be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT).
If more than one program (or task) is running on a processor, each program can be assigned its own set of
segments. The processor then enforces the boundaries between these segments and insures that one program
does not interfere with the execution of another program by writing into the other program’s segments. The
segmentation mechanism also allows typing of segments so that the operations that may be performed on a particular
type of segment can be restricted.
All the segments in a system are contained in the processor’s linear address space. To locate a byte in a particular
segment, a logical address (also called a far pointer) must be provided. A logical address consists of a segment
selector and an offset. The segment selector is a unique identifier for a segment. Among other things it provides an
offset into a descriptor table (such as the global descriptor table, GDT) to a data structure called a segment
descriptor. Each segment has a segment descriptor, which specifies the size of the segment, the access rights and
privilege level for the segment, the segment type, and the location of the first byte of the segment in the linear
address space (called the base address of the segment). The offset part of the logical address is added to the base
address for the segment to locate a byte within the segment. The base address plus the offset thus forms a linear
address in the processor’s linear address space.
3-2 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
If paging is not used, the linear address space of the processor is mapped directly into the physical address space
of processor. The physical address space is defined as the range of addresses that the processor can generate on
its address bus.
Because multitasking computing systems commonly define a linear address space much larger than it is economically
feasible to contain all at once in physical memory, some method of “virtualizing” the linear address space is
needed. This virtualization of the linear address space is handled through the processor’s paging mechanism.
Paging supports a “virtual memory” environment where a large linear address space is simulated with a small
amount of physical memory (RAM and ROM) and some disk storage. When using paging, each segment is divided
into pages (typically 4 KBytes each in size), which are stored either in physical memory or on the disk. The operating
system or executive maintains a page directory and a set of page tables to keep track of the pages. When a
program (or task) attempts to access an address location in the linear address space, the processor uses the page
directory and page tables to translate the linear address into a physical address and then performs the requested
operation (read or write) on the memory location.
If the page being accessed is not currently in physical memory, the processor interrupts execution of the program
(by generating a page-fault exception). The operating system or executive then reads the page into physical
memory from the disk and continues executing the program.
When paging is implemented properly in the operating-system or executive, the swapping of pages between physical
memory and the disk is transparent to the correct execution of a program. Even programs written for 16-bit IA-
32 processors can be paged (transparently) when they are run in virtual-8086 mode.

BTW, is a paging file "required" to work in this virtual environment?

it is a process towards learning

Asked another way

can linear address space point to the physical address space such that they are aligned the same, address 0 linear address space equals 0 physical memory address?

And still see the original contents prior to being placed in that virtual environment?

BTW, is a paging file "required" to work in this virtual environment?

simply make all virtual memory be "reloaded" as zeros (or some other fixed set of constant values) each time it is used