What will happen without 66

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l4m2

Joined: 15 Jan 2015
Posts: 666

l4m2

Code:

66 0F 58 D3 addpd  xmm2,xmm3

i think the 66 may be useless
Move to where, i dont know

21 Mar 2015, 15:27

Roman

Joined: 21 Apr 2012
Posts: 1219

Roman

i`ts joke ? Smile

66 0F 58 D3 this like number in list of CPU commands.
Another value and you get another CPU command

You like magic ? Very Happy

Last edited by Roman on 21 Mar 2015, 16:13; edited 1 time in total

21 Mar 2015, 16:12

CandyMan

Joined: 04 Sep 2009
Posts: 346
Location: film "CandyMan" directed through Bernard Rose OR Candy Shop

CandyMan

Code:

0F 58 D3 addps xmm2,xmm3

_________________
smaller is better

21 Mar 2015, 16:13

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 18723
Location: In your JS exploiting you and your system

revolution

x86 instruction encoding has evolved over time. There are many things in there that are weird and redundant. But for the time being we are stuck with it.

Last edited by revolution on 22 Mar 2015, 10:16; edited 2 times in total

21 Mar 2015, 16:26

l4m2

Joined: 15 Jan 2015
Posts: 666

l4m2

CandyMan wrote:

Code:

0F 58 D3 addps xmm2,xmm3

see
I first know 66 not only change between 16b 32

21 Mar 2015, 16:29

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 18723
Location: In your JS exploiting you and your system

revolution

This is a weird anomaly also:

Code:

xor eax,eax ;null pointer with Z flag set
cmovnz ecx,[eax] ;<--- crashes even when the condition is false

22 Mar 2015, 10:20

l4m2

Joined: 15 Jan 2015
Posts: 666

l4m2

revolution wrote:

This is a weird anomaly also:

Code:

xor eax,eax ;null pointer with Z flag set
cmovnz ecx,[eax] ;<--- crashes even when the condition is false

Don't you think it may read the [eax] in an earlier time if so?

22 Mar 2015, 10:31

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 18723
Location: In your JS exploiting you and your system

revolution

The error can be held pending and only allowed to propagate once the condition is known and evaluated. Other CPUs can do speculative memory reads in this way so in a technical sense there is no reason it couldn't have worked this way.

22 Mar 2015, 10:36

l4m2

Joined: 15 Jan 2015
Posts: 666

l4m2

revolution wrote:

The error can be held pending and only allowed to propagate once the condition is known and evaluated. Other CPUs can do speculative memory reads in this way so in a technical sense there is no reason it couldn't have worked this way.

If reading it before it can run faster and of course with a bit we can make it legal. Maybe Intel thought nobody run this but they were wrong because there are some code like

Code:

a=ptr?ptr[0]:0

(to put 0 easier)

22 Mar 2015, 10:40

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 18723
Location: In your JS exploiting you and your system

revolution

Notably missing is "cmovcc reg,imm".

22 Mar 2015, 10:45

AsmGuru62

Joined: 28 Jan 2004
Posts: 1457
Location: Toronto, Canada

AsmGuru62

Intel manual says that CMOVxx memory operand must be accessible.
Not sure about AMD.

22 Mar 2015, 11:48

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 18723
Location: In your JS exploiting you and your system

revolution

AsmGuru62 wrote:

Intel manual says that CMOVxx memory operand must be accessible.
Not sure about AMD.

The behaviour is the same for both. It is part of the spec. But it could have been much more useful. Sad

Last edited by revolution on 23 Mar 2015, 00:30; edited 1 time in total

22 Mar 2015, 16:37

HaHaAnonymous

Joined: 02 Dec 2012
Posts: 1178
Location: Unknown

HaHaAnonymous

Quote:

The behaviour is the same for both.

The behavior is the same but the performance differs. Usually in favor of Intel (see FPU, SSE and AVX).

One of the reasons "floating point" enthusiasts usually prefer Intel.

22 Mar 2015, 17:06

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