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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17248
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revolution
You can put a resistor in series to limit any fault currents to a safe level. 1Kohm would be a super safe value, but if that doesn't give enough drive signal then use 330ohm.
Post 04 Mar 2014, 09:24
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Do you mean something like the following?
Code:
5V_from_motherboard/3.3V_from_FGPA_board/5V_from_PSU
                    ___
                     |
                     Pull_up_from_motherboard/4.7K R
                     |
FPGA_pin--x--1K R----+-----FDD_output_pin
          |
          +--Probe_point    
Isn't the FPGA input pin supposed to consume almost no current in an input pin and hence the Probe_point measure almost 5V? Why wouldn't that be unsafe for the FPGA?
Post 04 Mar 2014, 15:13
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17248
Location: In your JS exploiting you and your system
revolution
The FDD output will just go through the 1k and into the FPGA VDD supply through the integral reverse diode on the input pin. That way it can work for both open collector and TTL outputs.

If you know that you have totem pole drivers then you can use a resistor divider and forget about the pullup and the current limit resistor.

If you know that you have open collector drivers then you can use just a pull-up resistor to the FPGA VDD supply.
Post 04 Mar 2014, 15:24
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Quote:
The FDD output will just go through the 1k and into the FPGA VDD supply through the integral reverse diode on the input pin.
Well, I'm not very convinced about this, basically, because I don't understand it Razz

Are level converters hard to find these days in electronic stores? (Can't order anything on Internet due to new imports regulations) I could try one of those if not. Also, maybe making my own open collector circuit with PNP switching transistors connecting base to the FDD cable would both be safe and reliable? That would probably inject little current to the FDD cable when LOW and also all currents would go to GND (something I can understand Razz), and I believe are easy to find (not sure if the characteristics I need, though).

Unless I'm lucky with the electronics store, I'd try the resistor divider first, with relatively high resistor values to attempt compatibility with both types of drivers while (probably) sacrificing signal integrity.

Thanks for your (what it seems to be) infinite patience Embarassed
Post 04 Mar 2014, 23:03
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Quick question: Are those negative voltage spikes real? Also, by using pull ups with smaller resistance I've seen voltage spikes closing to 4V on the FPGA side (even if I set all voltage sources to 3.3). Even if them are real, are them an actual threat to the FPGA when inputs are configured as LVCMOS? (It is an Spartan 6 which comes with the Nexys 3 board, and has no tolerance for 5V).

[edit]M2 is emulating the sink transistor inside the FDD, so is not actually part of the components I'd use.[/edit]


Description:
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Nexys3-PMod-Plug.jpg


Description:
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LTSpice.png


Post 27 Apr 2014, 15:56
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17248
Location: In your JS exploiting you and your system
revolution
Voltage spikes are caused by stray capacitance and inductance in the board and wiring. This is not a concern. When a pin is stated to not be 5V tolerant that means for a continuous 5V input signal that can provide a large energy dump and burn out the internal protection circuit. Brief spikes are easily absorbed by IC input pin protection. Such spikes are normal in all circuitry.

The thing to consider here is the total energy present, not the absolute voltages. If you have particularly large values of stray inductance and capacitance then the energy delivery will be larger. Most ICs made today are rated for 2kV input spike tolerance to accommodate for the "human body" model for static discharge.
Post 27 Apr 2014, 16:18
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LocoDelAssembly
Your code has a bug


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Posts: 4633
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LocoDelAssembly
OK, thanks! This is also true for negative voltages?

I hope I can start to get this done finally. Do you find my super amateur design suitable for reading the FDD data pin? I simulated there with a 2 MHz signal with 50ns pulses (the FDD goes LOW when a flux reversal is encountered, and 50ns is the minimum length 82077AA FDC supports). Also tried 25ns pulses and seems to be detectable as well. The real bandwidth should be 1mbps max, but I'm aiming for higher bandwidth and very short pulse detection in case my hypothesis that damaged bits might violate timing constraints is true.

I do not have an oscilloscope so LTSpice and testing with real hardware without measurements is the best I can do... I also hope those 2N7000/2 transistors are easy to find...
Post 27 Apr 2014, 17:11
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
OK, I managed to get ten 2N7000 transistors. Also I noticed later that the 1mbps bandwidth might only be needed for 3 1/2 floppies with capacities larger than 1.44 MB (which even use a different magnetic recording method but still using MFM). By chance I also got a FDD cable connector besides the pin headers (which is what I was actually expecting when I showed them the cable to show the required thickness and separation of the pins).

Hope I won't fry the FPGA in the process.

revolution, if you see any problem with the circuit above please let me know.


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2N7000AndStuff.jpg


Post 29 Apr 2014, 22:17
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17248
Location: In your JS exploiting you and your system
revolution
LocoDelAssembly wrote:
This is also true for negative voltages?
Yes.
LocoDelAssembly wrote:
revolution, if you see any problem with the circuit above please let me know.
You'll be fine. The highest risk to the FPGA is you when you touch it.
Post 30 Apr 2014, 08:26
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