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Index > Compiler Internals > mov seg_reg,reg32 not compiled

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jorom



Joined: 12 Dec 2004
Posts: 8
Location: Russia
jorom
Hello!

fasm 1.70 not compiled
Code:
mov seg_reg,reg32    


why?

older versions of fasm compile properly (fasm 1.48 for example)

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sorry for my english
Post 08 Apr 2013, 20:52
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baldr



Joined: 19 Mar 2008
Posts: 1651
baldr
jorom,

Probably because segment register is 16-bit-wide?
Post 08 Apr 2013, 22:53
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MazeGen



Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia
MazeGen
According to Intel manual, such operand combination is allowed: "When the processor executes the instruction with a 32-bit general-purpose register, it assumes that the 16 least-significant bits of the general-purpose register are the destination or source operand."
Post 09 Apr 2013, 09:30
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7802
Location: Kraków, Poland
Tomasz Grysztar
When you reverse the direction, there really are two different instructions:
Code:
mov ax,cs ; doesn't clear upper bits
mov eax,cs ; clears upper bits    
Try it out! Depending on your mode one of these instruction will be longer because of prefix, so when it doesn't matter to you it is better to use the native size (no prefix is generated there).

But when you move into the segment register, there is only one instruction, prefix doesn't matter. In this case fasm requires that you specify the actual data (16-bit register) that is used and no prefix is generated, no matter what mode you use.
Post 09 Apr 2013, 13:24
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MazeGen



Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia
MazeGen
I know this is a very minor issue but fasm behaves inconsistently here. MOV Sreg, gpr16 is actually assembled to MOV Sreg, grp32; MOV Sreg, gpr32 can't be assembled.

(Yes, as for the unmatching operand sizes the manual mentions only MOV Sreg, r/m64 so I assume the MOV Sreg, r/m32 is missing unintentionally)
Post 09 Apr 2013, 13:45
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7802
Location: Kraków, Poland
Tomasz Grysztar
MazeGen wrote:
I know this is a very minor issue but fasm behaves inconsistently here. MOV Sreg, gpr16 is actually assembled to MOV Sreg, grp32; MOV Sreg, gpr32 can't be assembled.
In my opinion there is no such instruction as "MOV Sreg, gpr32". Only the gpr16 portion is used. It does make sense in the opposite direction (though "MOV gpr32,Sreg" is in fact a MOVZX in disguise), but in the other case there is only one operation that you can really encode: "MOV Sreg, gpr16", and neither mode nor prefix change this operation.
Post 09 Apr 2013, 14:17
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MazeGen



Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia
MazeGen
Intel Instruction Set Reference, A-Z (325383-044US, August 2012) has MOV Sreg, r/m64 instruction, described as "Move lower 16 bits of r/m64 to segment register." The source gpr32 operand is mentioned below in the Description chapter, and IIRC it was always there.

I'm not saying fasm should strictly follow Intel syntax, however, we can't say there is no such instruction as "MOV Sreg, gpr32" when we can find it in the manual Smile
Post 09 Apr 2013, 17:50
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7802
Location: Kraków, Poland
Tomasz Grysztar
The main reason why syntax rules for the complete instruction set are documented in fasm's manual is that fasm's syntax does not always follow the rules from Intel or AMD manuals. With later instruction sets I sometimes give up and do not reinvent syntax to clear up the inconsistencies, but with the original 80386 instruction set I did some tweaking. For me there is no "MOV Sreg, gpr32" instruction, because you do not use the 32-bit register there (since, obviously, this data would not fit in destination), you use only 16-bit one, and this is what the instruction syntax should state.
Post 09 Apr 2013, 18:10
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