macro atomic_64_bit_read address {
        ;thread safe read 64-bit memory location. read edx:eax from memory
        ;ebx and ecx are corrupted
        mov     ebx,eax         ;in case of match place back the same value (non-destructive read)
        mov     ecx,edx         ;in case of match place back the same value (non-destructive read)
        lock cmpxchg8b address  ;value is returned in edx:eax (edx is high order 32 bits, eax is low order 32 bits)
}

macro atomic_64_bit_write address {
        ;thread safe write 64-bit memory location. write ecx:ebx to memory (ecx is high order 32 bits, ebx is low order 32 bits)
        ;edx and eax are corrupted
        local   .retry
    .retry:
        lock cmpxchg8b address  ;write ecx:ebx to memory if edx:eax matches current value
        jnz     .retry          ;if no match then try again with new value in edx:eax
}

macro atomic_64_bit_op address,op1,op2 {
        ;thread safe operation of edi:esi with the 64-bit memory location (edi is high order 32 bits, esi is low order 32 bits)
        ;eax, ebx, ecx and edx are corrupted
        ;firstly read the value in the memory location
        local   .retry
        atomic_64_bit_read address
    .retry:
        ;transfer to working registers ecx:ebx
        mov     ebx,eax
        mov     ecx,edx
        ;do the requested operation
        op1     ebx,esi
        op2     ecx,edi
        ;try to write it back
        lock cmpxchg8b address  ;write ecx:ebx to memory only if edx:eax matches current value (i.e. no one else has changed the value)
        jnz     .retry          ;if the memory value has changed then try again with new value in edx:eax
}

macro atomic_64_bit_add address { atomic_64_bit_op address,add,adc }
macro atomic_64_bit_sub address { atomic_64_bit_op address,sub,sbb }
macro atomic_64_bit_xor address { atomic_64_bit_op address,xor,xor }
macro atomic_64_bit_or  address { atomic_64_bit_op address, or, or }
macro atomic_64_bit_and address { atomic_64_bit_op address,and,and }
macro atomic_64_bit_inc address {
        xor     edi,edi
        mov     esi,1
        atomic_64_bit_add address
}
macro atomic_64_bit_not address {
        or      edi,-1
        or      esi,-1
        atomic_64_bit_xor address
}    

include 'win32ax.inc'
include 'atomic64.inc'

TEST_COUNT = 1000000

.data

        counter dq ?
        thread1 dd ?
        thread2 dd ?
        message rb 1024

.code

start:
        stdcall run_test,unsafe_thread
        stdcall run_test,safe_thread
        invoke  MessageBox,0,message,'Safe or not?',0
        invoke  ExitProcess,0

proc run_test uses edi ebx,address
        xor     ecx,ecx
        xor     ebx,ebx
        atomic_64_bit_write [counter]
        invoke  GetTickCount
        mov     edi,eax
        invoke  CreateThread,NULL,0,[address],TEST_COUNT,NULL,thread1
        mov     [thread1],eax
        invoke  CreateThread,NULL,0,[address],TEST_COUNT,NULL,thread2
        mov     [thread2],eax
        invoke  WaitForMultipleObjects,2,thread1,TRUE,-1
        invoke  GetTickCount
        sub     edi,eax
        neg     edi
        invoke  lstrlen,message
        invoke  wsprintf,addr message+eax,<'Count:%I64u Time:%u',13,10>,double [counter],edi
        ret
endp

proc safe_thread count
    .loop:
        atomic_64_bit_inc [counter]
        dec     [count]
        jnz     .loop
        ret
endp

proc unsafe_thread count
    .loop:
        mov     eax,dword[counter+0]
        mov     edx,dword[counter+4]
        add     eax,1
        adc     edx,0
        mov     dword[counter+0],eax
        mov     dword[counter+4],edx
        dec     [count]
        jnz     .loop
        ret
endp

.end start    

Count:1150857 Time:47
Count:2000000 Time:187    

proc unsafe_thread count
        mov eax,1
    .loop:
        lock
        add dword [counter+0],eax
        jnc @F
        add dword [counter+4],eax
@@:
        dec     [count]
        jnz     .loop
        ret
endp    

Code:

proc unsafe_thread count
    .loop:
        mov eax,1
        lock
        xadd dword [counter+0],eax
        jnc @F
        add dword [counter+4],1
@@:
        dec     [count]
        jnz     .loop
        ret    

...I wasn't able to break it with 16 threads.
Doesn't mean anything though.

Count:1982888850292736 Time:78
Count:2000000000000000 Time:187    

ADDER_VALUE     = 1000000000

proc safe_thread count
        mov     esi,ADDER_VALUE and 0xffffffff
        mov     edi,ADDER_VALUE shr 32
    .loop:
        atomic_64_bit_add [counter]
        dec     [count]
        jnz     .loop
        ret
endp

proc unsafe_thread_bitRAKE count
    .loop:
        mov     eax,ADDER_VALUE
        lock
        xadd    dword[counter+0],eax
        jnc     .skip
        add     dword[counter+4],1
    .skip:
        dec     [count]
        jnz     .loop
        ret
endp    

(You change it to make it fail.)

_counter dd counter

proc safe_thread count

.loop:
        xor ecx,ecx
@@:     xchg ecx,[_counter]
        jecxz @B

        add dword [ecx+0],1
        adc dword [ecx+4],0

        mov [_counter],ecx

        dec     [count]
        jnz     .loop
        ret
endp
; cmpx: 4302467295 Time:842
; xchg: 4302467295 Time:2090    

The lock cmpxchg8b method is considerably faster than using xchg:

mov eax, 1
lock xadd [mem], eax
    

Very fast and simple atomic increment:

Code:

mov eax, 1
lock xadd [mem], eax
    

Adds one to [mem] and returns previous value stored in [mem].

This lockless method is consistently faster on my system. Not as complex as it looks - bit lock on pieces and partitioned the counter into 16 pieces. Each thread operates on the opposite bit state. This is done so that each thread isn't just counting by itself - that would be too easy. So, there is actual forced contention for resources.

Edit: I should also say that it's guaranteed to work because of memory ordering rules on the bus.

Sorry, I made an edit. It is guaranteed to work. Vol3, Ch8 in the manual explains the memory ordering rules. It's lockless in that a LOCK# signal is not sent across the bus. Which can have a huge impact in performance. It's not a small gain - it can be over twice faster.

Unless Intel is lying in the manual then it should work in general (Pentium+). I've been using Dual socket mobos since my overclocked BP6.

READ A.1.1
READ A.1.0
        READ B.1.0
        READ C.1.0
        WRITE B.1.0
        WRITE C.1.0
        READ A.1.0
        WRITE A.1.0

READ A.2.0
READ A.2.1
        READ B.2.1
        READ C.2.1
        WRITE B.2.1
        WRITE C.2.1
        READ A.2.1
        WRITE A.2.1