[ARM] 64 bit two's compliment

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Index > Non-x86 architectures > [ARM] 64 bit two's compliment

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cwpjr

Joined: 03 Jul 2012
Posts: 44

cwpjr 27 Oct 2012, 23:03

I am sorry to bother you folks with my problem. That said I am trying to figure out in THUMB2 code how to take MSW LSW 64 bit double word ( say in r1 and r2 ) value that could be signed or not and convert the whole shebang to a double number two's complement of the original value.

Baring puppy love in code an explanation of the logic would be fine...

Thanks, Clyde

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27 Oct 2012, 23:03

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20623
Location: In your JS exploiting you and your system

revolution 28 Oct 2012, 00:20

The most common way to do extended two's complement is negate and add 1:

Code:

mvn  r1,r1
mvn  r2,r2
adds r1,r1,1
adc  r2,r2,0

28 Oct 2012, 00:20

cwpjr

Joined: 03 Jul 2012
Posts: 44

cwpjr 28 Oct 2012, 00:59

Thank Revolution. I still haven't forgotten your challenge of x86 translation but I am not up to te task yet!

28 Oct 2012, 00:59

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