flat assembler
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> OS Construction > IDT problem |
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edfed 06 Apr 2012, 23:39
you should implement the 32 first interrupt vectors as they are reserved for the cpu in protected mode. here, you just have defined the 9 first vectors, it's not enough.
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06 Apr 2012, 23:39 |
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dilipcs1992 07 Apr 2012, 04:01
edfed wrote: you should implement the 32 first interrupt vectors as they are reserved for the cpu in protected mode. here, you just have defined the 9 first vectors, it's not enough. no i have defined 32 interrupt vectors but i have posted only some part of the code |
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07 Apr 2012, 04:01 |
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cod3b453 07 Apr 2012, 12:38
Only double fault or does it triple fault as well?
Do you know what the first exception was? Is paging enabled? Is the pop ebx in the ISRs correct? |
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07 Apr 2012, 12:38 |
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edfed 07 Apr 2012, 14:29
cod3b453 wrote: Is the pop ebx in the ISRs correct? effectivelly, this instruction seems to unbalance the stack. |
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07 Apr 2012, 14:29 |
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smiddy 07 Apr 2012, 15:55
edfed wrote:
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07 Apr 2012, 15:55 |
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dilipcs1992 07 Apr 2012, 16:35
cod3b453 wrote: Only double fault or does it triple fault as well? first exception is bound range exceeded only double fault exception, no triple fault paging is not enabled yes i removed pop ebx instruction.still same result |
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07 Apr 2012, 16:35 |
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16bitPM 07 Apr 2012, 20:04
dilipcs1992 wrote:
Probably a silly question, but since you suggested that you are writing boot code: are you already in protected mode? |
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07 Apr 2012, 20:04 |
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flash 08 Apr 2012, 01:47
Well, may be the problem is not in your initialization code, but at the "operational" code. What are you doing after setting idtr and gdtr?
Take care about implicit ds or ss usages, it is possible you are using incorrect values at those registers. I recommend you to write a valid descriptor for int 13(general protection fault). It is highly probable it clarifies the bugs: codes: bits 0 and 1 INDEX: bits 3 up to end(like selectors) bit 0. 1:External source 0: internal source bit 1. 1:INDEX is the index of idt that cause the fault 0: index is the gdt index where the fault occurs. |
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08 Apr 2012, 01:47 |
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dilipcs1992 08 Apr 2012, 11:39
flash wrote: Well, may be the problem is not in your initialization code, but at the "operational" code. What are you doing after setting idtr and gdtr? after setting gdt and idt i just print Hello World string. after setting valid idt descriptor General protection fault is causing double fault exception |
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08 Apr 2012, 11:39 |
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BAiC 11 Apr 2012, 15:02
FYI: executing a halt (hlt) with the interrupt flag cleared causes a processor freeze that can only be recovered with an advanced NMI/SMI... not sure why you've included it though.
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11 Apr 2012, 15:02 |
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shutdownall 11 Apr 2012, 21:08
dilipcs1992 wrote:
Maybe this is because you get interrupts ? Did you try to disable interrupt controller ? Maybe you get an interrupt not catched. Did you try to disable PIC with the specified I/O addresses ? |
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11 Apr 2012, 21:08 |
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dilipcs1992 19 Apr 2012, 18:48
yes when i disable irqs
everything is working fine, but when i enable irqs i get GP# |
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19 Apr 2012, 18:48 |
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shutdownall 20 Apr 2012, 13:03
I think (as is in my mind) you can not disable the exceptions or "traps" (IRQ 0-1F).
So must be a "real" interrupt not catched from a real time clock or something similar. Try to catch all interrupts 00-FF and check which interrupt occurs and why. Did you check all hints in the INTEL documentation "IA32 Software Development Guide Vol. 3a" ? Chapter 6 describes detailed interrupt system and how to be handled on about 65 pages. |
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20 Apr 2012, 13:03 |
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BAiC 24 Apr 2012, 04:30
perhaps it's in the code you didn't publish? "puts" isn't provided, for one.
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24 Apr 2012, 04:30 |
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smiddy 24 Apr 2012, 11:11
Here's my IDT, hopefully it will provide you with what you need. Beware, it is circa 2005 and may not be as up to date as it could be, although it still assembles and works:
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24 Apr 2012, 11:11 |
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