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yoshimitsu



Joined: 07 Jul 2011
Posts: 96
yoshimitsu
Hi there,
I was just a little wondering about the following:

for example psubb, psubw, psubd and psubq have a consecutive opcode (F8, F9, FA, FB), paddb, paddw, paddd and paddq, however, have not (FC, FD, FE, D4). Why is that?

additionally, for mmx instructions the 66h-prefix is used for their sse pendants, however, there are many instructions which operate only on sse registers like roundpd, though, they have a preceding mandatory prefix, although it's often the only valid encoding for this opcode. Why is such instruction unnecessarily bigger than it could be?

another thing, why are e.g. roundss and roundsd encoded with different opcodes? I mean there's apparently enough room to do so, but wouldn't it be possible to switch through them via 66-/F2-/F3-prefixes like it's done with many 2-byte opcodes?
Post 19 Mar 2012, 23:14
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17666
Location: In your JS exploiting you and your system
revolution
You are asking in the wrong place. Ask Intel and/or AMD, they designed it.
Post 20 Mar 2012, 01:39
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17666
Location: In your JS exploiting you and your system
revolution
If I was to guess at why paddq is encoded as D4 instead of FF it would be because of OIO being FF also. OIO is from the old Cyrix CPU manual and stands for Official Invalid Opcode. Of course now UD2 is the standard. But like I said above, I am only guessing and if you want the real reasons then only direct from the designers is going to be the best chance of getting a real answer.

See here also:

http://board.flatassembler.net/topic.php?t=4069
Post 20 Mar 2012, 12:27
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yoshimitsu



Joined: 07 Jul 2011
Posts: 96
yoshimitsu
ok, thanks. I just thought there might be some logical reasons which I overlooked or that maybe someone would know.
Post 20 Mar 2012, 13:32
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