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Teehee



Joined: 05 Aug 2009
Posts: 568
Location: Brazil
Teehee
this is part of ADC instruction from intel manual:

Code:
;op1 op2     opcode
ax    imm16   15 iw
r/m16  imm16   81 /2 iw    


(case 1)

Code:
;           opcode
adc ax, 1     15 01 00
adc ax, 1   83 D0 01    


That means that these builds are equivalents and they will result in the same result?

(case 2)

Code:
ax     imm16   15 iw
eax    imm32   15 id    

How will the processor know that in the first line it will need to read a word, and in the second one a dword? (by the 66 prefix?)

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Sorry if bad english.
Post 09 Feb 2012, 17:23
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17474
Location: In your JS exploiting you and your system
revolution
Teehee wrote:
Code:
ax      imm16   15 iw
eax    imm32   15 id    

How will the processor know that in the first line it will need to read a word, and in the second one a dword? (by the 66 prefix?)
Yes. And also the current processor mode will define which register size to use. Don't forget about RAX also.
Post 09 Feb 2012, 17:41
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17474
Location: In your JS exploiting you and your system
revolution
BTW: There are many functionally equivalent encodings in x86. An assembler is free to choose which one it wants to generate.
Post 09 Feb 2012, 17:44
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