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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
i still don't understand:
expression "bswap 1234h" should result in 3412000000000000h, and "dword <expression>" should truncate result of expression to 32bits, so how does it work?
Post 10 May 2004, 18:35
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7796
Location: Kraków, Poland
Tomasz Grysztar
The way expression is calculated depends on the predicted output size, because if you have done some logical operations on the small values extended to 64-bit and then wanted to fit it into small value, it might happen that value would no fit in smaller amount of bits. For example "not 8Fh" performed on 64-bits is the same as "-90h" value, and so "db not 9Fh" would cause "value out of range" error. But fasm knows that argument to the "db" directive has to be 8-bit value, so when it calculates "not", does it only on the low 8 bits.

Every time an expression calculator is used, it needs to have specified the size of the output value it has to make, so it can adjust those operations appropriatelly. And so for "mov eax,not 8Fh" is does operation on the 32 bits, and for "mov al,not 8Fh" on the 8 bits. In case of numerical constant definition, default size is the maximum (64 bits), so this code:
Code:
const = not 8Fh
db const    

will fail, the constant has 64-bit value of -90h, which cannot fit in the byte. But you can adjust the size of value you want to get with the size operator:
Code:
const = byte not 8Fh
db const    

in this case the logical "not" was performed on 8 bits only, and constant got value 70h this way.

How it was adapted for the intended "bswap" behavior, it is simple, I think.
Post 10 May 2004, 19:12
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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
so, i thought size operator in expressions is just truncation, now i see it has more special role.
Post 11 May 2004, 06:56
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comrade



Joined: 16 Jun 2003
Posts: 1137
Location: Russian Federation
comrade
Was this feature ever officially implemented? My memory was sparked by http://board.flatassembler.net/topic.php?t=2005

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Post 08 Aug 2004, 00:45
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Matrix



Joined: 04 Sep 2004
Posts: 1171
Location: Overflow
Matrix
Code:

bswapw:
xchg al,ah
ret

bswapd:    ; 01 23 45 67
xchg al,ah ; 01 23 67 45
rol eax,16 ; 45 67 01 23
xchg al,ah ; 45 67 23 01
ret                   

This is very easy Smile

    



MATRIX
Post 11 Sep 2004, 10:22
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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
In 32bit mode it is very slow and also xchg is very clumsy.
Code:
bswapd:                ; 01234567h
    mov ebx,eax        ; 01234567h
    rol eax,8          ; 23456701h
    ror ebx,8             ; 67012345h
    and eax,000FF00FFh ; 00450001h
    and ebx 0FF00FF00h ; 67002300h
    or  eax,ebx        ; 67452301h
ret
    

much faster, at least in my tests Razz
-BUT- uses two registers

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Post 11 Sep 2004, 11:05
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Matrix



Joined: 04 Sep 2004
Posts: 1171
Location: Overflow
Matrix
Madis731 wrote:
In 32bit mode it is very slow and also xchg is very clumsy.
Code:
bswapd:                ; 01234567h
    mov ebx,eax        ; 01234567h
    rol eax,8          ; 23456701h
    ror ebx,8             ; 67012345h
    and eax,000FF00FFh ; 00450001h
    and ebx 0FF00FF00h ; 67002300h
    or  eax,ebx        ; 67452301h
ret
    

much faster, at least in my tests Razz
-BUT- uses two registers



Smile
yes, my poing was exactly to emulate the cpu function withoust using memory or other registers
but its nice code you have there

MATRIX
Post 11 Sep 2004, 13:21
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S.T.A.S.



Joined: 09 Jan 2004
Posts: 173
Location: Ru#27
S.T.A.S.
Yes, bswap is slow on Pentium IV (very *advanced* CPU :/) - this is documented by intel.
Post 11 Sep 2004, 19:54
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comrade



Joined: 16 Jun 2003
Posts: 1137
Location: Russian Federation
comrade
what about the directive itself? is it in fasm?
Post 12 Sep 2004, 00:10
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Matrix



Joined: 04 Sep 2004
Posts: 1171
Location: Overflow
Matrix
Madis731 wrote:
In 32bit mode it is very slow and also xchg is very clumsy.
Code:
bswapd:                ; 01234567h
    mov ebx,eax        ; 01234567h
    rol eax,8          ; 23456701h
    ror ebx,8             ; 67012345h
    and eax,000FF00FFh ; 00450001h
    and ebx 0FF00FF00h ; 67002300h
    or  eax,ebx        ; 67452301h
ret
    

much faster, at least in my tests Razz
-BUT- uses two registers


Hy again,
that is might be because newer CPU's can do more of the primitive operations in one tick, that's nice, getting closer to RISC architecture
the bad news is there are some instructions can't be run together, and there can be many trouble making some code faster.
there are some C compilers which make this for you - for example new microcontrollers are RISC. But these compilers are at a very high cost !


MATRIX
Post 15 Sep 2004, 18:26
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