Say hello to a new instruction RDRAND, Random number generator.

Here is the full changes post: http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developers-manual.html?wapkw=developers%20manual
Page 9

PS: Requires flash.

Thanks for your report, Do you know which set of processors support this instruction

In that same manual there is a CPUID bit described as indicating the instruction presence.

There's a chapter somewhere at the beginning of the manual that lists processors covered by the manual. Therefore, if the manual introduces new instruction, the most recent processor mentioned in the list should be the first one that supports it. There may be exceptions to this rule, of course.

> Intel has added a new instruction Kewl !

COOL What does the new KEWL instruction do ?

> PS: Requires flash.

I see ... or not ... I can't download anything from them. Intel brings hot compatibility breaking technology again

DOS386
http://www.urbandictionary.com/define.php?term=kewl I know, you're just trolling ^^

Crap, now my processor requires Flash? WTF!

So how do we use? FASM doesn't support it yet, so what's the opcode for it along with the parameters?

Direct link to PDF:

http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-software-developers-manual.pdf It is explained in the doc.

Not true. It is supported since 1.69.15

version 1.69.15 (Aug 24, 2010)

[+] Added support for AVX, AES, PCLMULQDQ, FMA, RDRAND, FSGSBASE, F16C, FMA4
and XOP instruction sets.

1 year ago ... this was HOT news

> Page 9

NO. Page 11.

> so what's the opcode for it along with the parameters?

$0F, $C7, $F0 (latter for AX / EAX as operand)

Sad it hadn't been in since 8086

Anyone has an idea how much power or how many transistors it costs ?

I wonder what do they use for Nondeterministic random bit generator. Anyone has an idea?

Radioactive decay ??? Oops, it produces heat, Alpha or Beta + Gamma radiation, besides nondeterministic behavior

I once was a part of a project (1989, I believe) where RNG was done using the delays of a simple OR,AND elements. The fact is that delays between two pulses are not the exactly same - they differ in a miniscule sense, however some are smaller than average and some are larger. It may depend on a number of factors: background radiation levels, sun exposure, cosmic rays, temperature, magnetism, etc. So, basically, very presice pulse generator counts the size of delays and random sequence may be generated. Also, inside the device - the flow of delays can change - it may go through a different set of elements every time a number is generated. I wrote a self-test routine for this to detect if device is working properly.

Usually the thermal noise across a resistor is the easiest way to generate non-determinism. It is also an easy circuit to make both in the nanometre silicon and the discrete domains. The only real problem with it is the proper way to ensure you don't sample too fast and start getting poor quality bits. Intel seemed to have solved this with a PRNG following the RNG to create higher bandwidth number generation.

I liked the use of RDTSC instruction to get randomized values...

Yeah, and it worked also. But only if your read timings were already random. And only if you throw away the top bits and only use the low few bits. And only if a virus has not put you in hypervisor mode and is manipulating the counter value. Plus, doing that many times in a small loop is generally not a good way to generate high quality randomness.

I hope you haven't been dealing with cryptography.

Don't worry, I haven't been dealing with cryptography (fortunately). But before that new instruction, programmers had to work with rdtsc only?