Index
> OS Construction > IO APIC |
| Author |
|
|
cod3b453 23 Jun 2011, 17:34
The IOAPIC doesn't have an enable register but you should check for its existence (there shouldn't be one unless you have at least one LAPIC).
The LAPIC has enable bits in the base address and spurious interrupt registers. You should check CPUID for the presence of APIC and x2APIC before setting these. Once enabled, you can test the features register for extended mode and enable that. (Both Intel and AMD CPU manuals cover this) |
|||
23 Jun 2011, 17:34 |
|
|
BOTOKILLER 24 Jun 2011, 08:48
So , I have to enable IO APIC through LAPIC???
|
|||
|
24 Jun 2011, 08:48 |
|
|
DJ Mauretto 24 Jun 2011, 09:24
Hello
The I/O APIC is part of chipset , Local APIC is part of cpu. to play with I / O APIC you will need the datasheet of your chipset ( Southbridge)  _________________ Nil Volentibus Arduum  |
|||
|
24 Jun 2011, 09:24 |
|
|
BOTOKILLER 24 Jun 2011, 09:43
Yeah, thats exactly where I got the IO APIC register list - ICH 8 specs, but not a word there about how to turn IO APIC and use it instead of PIC...
Also, I found MADT table in ACPI, and found amount of IO APICs, what next??? |
|||
|
24 Jun 2011, 09:43 |
|
|
DJ Mauretto 24 Jun 2011, 12:03
Enable NMI, INTR from APIC
Code: Mov al,70h out 22h,al Mov al,01h out 23h,al For more information read Intel Multiprocessor specification Version 1.4 _________________ Nil Volentibus Arduum |
|||
|
24 Jun 2011, 12:03 |
|
|
BOTOKILLER 02 Jul 2011, 16:09
DJ Mauretto wrote: Enable NMI, INTR from APIC I searched a few days and finally i found way to turn on LAPIC - in Intel's CPU docs volume 3, I also looked in MP specs(even made my code to parse MP tables), there is even example in asm how to implement wirtual wire, but I want my OS to work in symmetric IO mode and also I need to know how to enable IO APIC........ I need more help...  |
|||
|
02 Jul 2011, 16:09 |
|
|
DJ Mauretto 03 Jul 2011, 09:42
Hello
To Enable I/O APIC Read Section 7.1.64 page 262 of Intel ICH 8 spec. There is a Register - OIC—Other Interrupt Control Register - BIt 0 of this register control I/O APIC. APIC Enable (AEN) — R/W. 0 = The internal IOxAPIC is disabled. 1 = Enables the internal IOxAPIC and its address decode. This is valid only for your chipset. Before you must read the base adress of Root Complex in PCI Config space at Device 31 Function 0 (LPC Interface) at offset F0 there is a register called Root Complex Base Address, then you must add offset of OIC—Other Interrupt Control Register - to the base address and change the bit of APIC enable. Code: Root_Complex_Base_Address DD ? mov esi,[Root_Complex_Base_Address] add esi,31ffh ; 31ff = offset OIC mov al,[esi] or al,1 ; Enable I/O APIC mov [esi],al _________________ Nil Volentibus Arduum |
|||
|
03 Jul 2011, 09:42 |
|
|
BOTOKILLER 03 Jul 2011, 13:10
DJ Mauretto wrote: Hello I found that yesterday evening(7.1.66), but i thought that 31FF - port number  so, Thanks!
P.S. How to map IO APIc ints??? |
|||
|
03 Jul 2011, 13:10 |
|
|
DJ Mauretto 03 Jul 2011, 16:42
Quote: I found that yesterday evening(7.1.66), but i thought that 31FF - port number Razz Embarassed so, Thanks! Maybe it's better that you learn a little bit more before to code a OS _________________ Nil Volentibus Arduum |
|||
|
03 Jul 2011, 16:42 |
|
|
BOTOKILLER 04 Jul 2011, 08:36
DJ Mauretto wrote:
I learn as I code ,
But how do I map IO APIC interrupts??? |
|||
|
04 Jul 2011, 08:36 |
|
|
DJ Mauretto 04 Jul 2011, 10:18
Quote: But how do I map IO APIC interrupts??? It is documented in the spec of your chipset, start doing some simple tests to understand the behavior of I/O APIC. _________________ Nil Volentibus Arduum |
|||
|
04 Jul 2011, 10:18 |
|
|
cod3b453 13 Jul 2011, 18:51
(You can also find this in the IOAPIC specification section 3)
There are two registers in the IOAPIC MMIO space that you use to program the type, vector and target CPU. |
|||
|
13 Jul 2011, 18:51 |
|
|
ouadji 13 Jul 2011, 20:05
http://www.intel.com/design/chipsets/datashts/290566.htm http://www.intel.com/assets/pdf/datasheet/319973.pdf Code: proc getINTfromIRQ IRQ:DWORD ;==================== cmp [flag_ioapic_mapped],TRUE jne .not_mapped push ecx edi mov ebx,[IRQ] mov edi,[mapped_IOAPIC_base] ;-----> proc Map_IOAPIC_HPET lea ecx,[(ebx*2)+10h] ;82093AA IOAOIC 3.2.4 (290566-001) mov [edi],ecx ;IO_APIC[0] = IOREGSEL mov eax,[edi+(4*4)] ;IO_APIC[4] = IOWIN inc ecx ;Results mov [edi],ecx ;------- mov ebx,[edi+(4*4)] ;eax = IOREDTBL dword_1 (INT = al) ;ebx = IOREDTBL dword_2 pop edi ecx stc retproc .not_mapped: mov eax,-1 clc retproc endp ;—————————————————————————————————————————————————————————————————————————————— proc Map_IOAPIC_HPET ;====================== locals phys_HPET dd ? phys_LAPIC dd ? ;0xFFFE0000 (0xFEE00000 mapped) ;0xFFFE00B0 hard-coded/halmacpi.dll phys_IOAPIC dd ? endl pushad ;------------------------------------------------------------------------- mov eax,1 cpuid bt edx,9 ;LAPIC présent ? jnc @F ;fail/noAPIC xor ebx,ebx mov ecx,IA32_APIC_BASE ;IA32_APIC_BASE = 1Bh rdmsr bt eax,11 ;APIC global enable/disable jnc @F mov ebx,eax and ebx,not 0xFFF @@: mov [phys_LAPIC],ebx ;physical Local_APIC ;------------------------------------------------------------------------ invoke KeGetCurrentIrql cmp eax,DISPATCH_LEVEL ja .fail_ ;fail/BadIRQL ;------------------------------------------------------------------------ ;RCBA (Root Complex Base Address Register ICH10/9.1 Table 9-1 ;ICH10/13.1.36) ;bus:0 device:31 function:0 Offset:F0 ; ; 1 0000000 00000000 11111 000 11110000 --> = ;0x8000F8F0 ;31 | 30 .. 24 | 23 .. 16 | 15 .. 11 | 10 ... 8 | 7 .. 0 ; 1 | reserved | n° bus | device | fonction | offset ;(max-->) FFh 1Fh 07h FFh mov dx,0CF8h mov eax,0x8000F8F0 out dx,eax mov dx,0CFCh in eax,dx ;physical RCBA and eax,0xFFFFC000 add eax,0x3000 ;max=0x35F3 ICH10/10.1 invoke MmMapIoSpace, eax, 0, PAGE_SIZE, MmNonCached cmp eax,NULL je .fail_ mov ebx,[eax+0x0404] ;0x3404 HPTC ICH10/10.1.74 ; bt ebx,7 ; jnc .fail_ and ebx,0011b shl ebx,12 or ebx,0xFED00000 mov [phys_HPET],ebx ;physical HPET movzx ebx,byte[eax+0x01FF] ;0x31FF FEC0x000h x=APIC Range ICH10/10.1.69 and bl,11110000b ;<=== x [4:7] shl ebx,8 or ebx,0xFEC00000 mov [phys_IOAPIC],ebx ;physical IOAPIC invoke MmUnmapIoSpace, eax, PAGE_SIZE ;------------------------------------------------------------------------------ invoke MmMapIoSpace, [phys_HPET], 0, PAGE_SIZE, MmNonCached cmp eax,NULL je .fail_ mov [mapped_HPTE_base],eax stop mov [flag_hpet_mapped],TRUE ;------------------------------------------------------------------------------ invoke MmMapIoSpace, [phys_IOAPIC], 0, PAGE_SIZE, MmNonCached cmp eax,NULL je .fail_ mov [mapped_IOAPIC_base],eax mov [esp+1Ch],eax mov [flag_ioapic_mapped],TRUE popad stc retproc .fail_: popad clc retproc endp ;phys_IOAPIC_base = FEC0x000h->FEC0x040h (Consumer Only) ICH10R ;"x" is controlled via APIC Range Select (ASEL) and APIC Enable (AEN) bit ;—————————————————————————————————————————————————————————————————————————————— |
|||
|
13 Jul 2011, 20:05 |
|
|
Mac2004 31 Dec 2011, 08:02
http://forum.osdev.org/viewtopic.php?f=1&t=24439
Here is a discussion about enabling ioapic along with my example. Regards Mac2004 |
|||
|
31 Dec 2011, 08:02 |
|
< Last Thread | Next Thread > |
Forum Rules:
|