ouadji
Joined: 24 Dec 2008
Posts: 1081
Location: Belgium
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INTEL 3A/2.3
... If an application program sets the TF flag using a POPF, POPFD, or IRET instruction,
a debug exception is generated after the instruction that follows the POPF, POPFD, or IRET
false, not in all cases.
mov ebx,dr7
bts ebx,13
mov dr7,ebx
pushfd
bts dword[esp],8
popfd
;--(abc)--> here (single step exception)
mov eax,dr6
;---------> NOT here
;stack at "abc"
;--------------
; flags
; cs
; eip -----> mov eax,dr6
;my_handler (dr6=0xFFFF6FF0)
;iret (back to "mov eax,dr6")
;and only AFTER that ... debug register access exception.
In this case, the "single step exception" is triggered before
the instruction that follows the "popfd", not after.
I looked everywhere in the Intel manuals,
I found nothing about this particular case.
However, I checked it myself, and it works exactly like that.
_________________ I am not young enough to know everything (Oscar Wilde)- 
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