flat assembler
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edfed 11 Mar 2011, 20:38
the lines you are speaking about are BUSes
there are 3 BUSes out of a CPU (every CPU in the Von neumann architecture). DATA bus ;64 wires Adress bus ;depend on implementation, mainly 32-3 bits (4Gbytes), and in IA32-64, mainly 64Gbytes. Control bus ;depend on implementation adress bus is emitted by CPU, and just gives the signal of WHAT adress in RAM to act on. data bus is controled by CPU and (theorically) RAM control bus is controled by CPU, peripherals and others things. used to say, read, write, I/Oports, irq, etc... |
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neville 11 Mar 2011, 20:57
You should google "CPU Architecture" for more info.
This diagram illustrates edfed's response but for an 8-bit CPU with only an 8-bit address bus too, so it could only support 2^8 = 256 bytes of RAM and also 256 I/O ports. One of the control bus lines is RW Read/Write which sets the direction of the bidirectional data bus buffers, either into (Read) or out of (Write) the CPU. Another control line on Intel CPU's is IO/M which selects IO port buffers or RAM. CPU's with pure memory-mapped I/O architectures don't have this.
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revolution 24 Mar 2011, 02:24
Note that later CPU interconnect architectures are much more complex. The traditional parallel buses (as shown above) are becoming less common and in some systems have been completely replaced by new types. So, check your system hardware first before assuming you have such a bus.
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