2. how many push/pop can i use before i consider to change to pusha/popa?

4. in PMode, do i really need to define a IDT and a PIT - System Clock? (check link please)

Completely up to you.

push eax
push ebx
push ecx ; 5 pushs
push edx
push esi
pop esi
pop edx
pop ecx ; 5 pops
pop ebx
pop eax    

pusha
popa    

... isn't slower than just ...?

pusha/popa exist only on few cpus, since 80386. removed in long mode.

pusha/popa exist only on few cpus, since 80386. removed in long mode.

;Source: Agner Fog's instruction_tables.pdf
         fused uops  p015 ... p3     p4      lat 1/throughput
PUSH reg      1              1       1       3       1
PUSHF(D/Q) 17      15      1       1               7
PUSHA(D)   18       9      1       8               8
    

For simplicity I'll take a 45nm Intel CPU (Wolfdale) for this example:

Code:

;Source: Agner Fog's instruction_tables.pdf
    fused uops  p015 ... p3     p4      lat 1/throughput
PUSH reg      1              1       1       3       1
PUSHF(D/Q) 17      15      1       1               7
PUSHA(D)   18       9      1       8               8
    

If you add up pushing of eax, edx, ecx, ebx, esi, edi, ebp then you will
get 7 uops in a fused domain, but adding the additional 3 clocks of
latency will take about 10 clocks of your precious CPU time.
When you use pusha, you will use 17 clocks.

On a Pentium MMX it used to take 5-9 clocks, on a Pentium III: 8 (or 10?) clocks. It has been around 17 clocks starting from Pentium M.

Sometimes breaking up instructions into smaller pieces will be faster.

macro push_all
{
; I hope this is correct, I followed Intel's Instruction Set Reference 2B
     mov     [esp-32],edi ;if esp-32 happens to fall at the start of cache line
  mov     [esp-28],esi ;then this instruction will surely cache following instructions
        mov     [esp-24],ebp
        mov     [esp-20],esp
        mov     [esp-16],ebx
        mov     [esp-12],edx
        mov     [esp-08],ecx
        mov     [esp-04],eax
        sub     esp,32 ; esp is only modified once
}
    

what is you get interrut in the middle of moving data?

macro push_all
{
; I hope this is correct, I followed Intel's Instruction Set Reference 2B
        sub     esp,32 ; esp is only modified once
        mov     [esp+0],edi ;if esp-32 happens to fall at the start of cache line
        mov     [esp+4],esi ;then this instruction will surely cache following instructions
        mov     [esp+8],ebp
        mov     [esp+12],esp
        mov     [esp+16],ebx
        mov     [esp+20],edx
        mov     [esp+24],ecx
        mov     [esp+28],eax
}     

sub esp before, then, no problem with interrupts

add dword[esp+12],32
    

push eax
; what if interrupt happens here and totally trashes ESP?
pop eax