flat assembler
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> Compiler Internals > [opcodes suggestion]MULB, DIVB |
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revolution 12 Feb 2011, 18:18
Code: mulb equ aad divb equ aam |
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12 Feb 2011, 18:18 |
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edfed 12 Feb 2011, 18:44
none.
Code: mulb equ byte 0D4h divb equ byte 0D5h aad equ mulb,10 aam equ divb,10 something like this, because AAM and AAD are composed by the opcode 0D4h/0D5h followed by immediate value 10 |
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12 Feb 2011, 18:44 |
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revolution 12 Feb 2011, 18:59
Did you try it? It works:
Code: mulb equ aad divb equ aam mulb 5 divb 34 |
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12 Feb 2011, 18:59 |
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edfed 12 Feb 2011, 19:13
cool, then, no more need for this mnemonic operation.
i suggested it just because some reading about instruction set pointed me this fact. |
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12 Feb 2011, 19:13 |
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ouadji 12 Feb 2011, 19:40
bscc brcc bccc (bit set/reset/complement if conditions) Code: bsnz eax,12 |
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12 Feb 2011, 19:40 |
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revolution 12 Feb 2011, 19:42
ouadji wrote: bscc brcc bccc (bit set/reset/complement if conditions) |
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12 Feb 2011, 19:42 |
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ouadji 12 Feb 2011, 19:47
I am a programmer not a microprocessor designer. and also the semiconductors implantation ? |
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12 Feb 2011, 19:47 |
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revolution 13 Feb 2011, 01:38
ouadji wrote: I am a programmer not a microprocessor designer. edfed was suggesting an alternate mnemonic for an existing opcode, which is easily doable with fasm. You appear to be suggesting completely new opcodes that the CPU doesn't have. |
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13 Feb 2011, 01:38 |
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ouadji 13 Feb 2011, 10:56
Quote: You appear to be suggesting completely new opcodes that the CPU doesn't have. i see no need and no utility to create an alternate mnemonic for an opcode that already exists. |
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13 Feb 2011, 10:56 |
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revolution 13 Feb 2011, 12:10
ouadji wrote: i see no need and no utility to create an alternate mnemonic for an opcode that already exists. |
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13 Feb 2011, 12:10 |
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ouadji 13 Feb 2011, 16:39
the exception that proves the rule ? hummm ... another one ? |
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13 Feb 2011, 16:39 |
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revolution 13 Feb 2011, 16:50
JA == JNBE
There are more. Lots more. |
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13 Feb 2011, 16:50 |
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edfed 13 Feb 2011, 18:10
retn = ret
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13 Feb 2011, 18:10 |
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