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Index > Compiler Internals > [opcodes suggestion]MULB, DIVB

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edfed



Joined: 20 Feb 2006
Posts: 4240
Location: 2018
edfed
Byte MULtiply:
MULB imm8
D5h,0Ah => AAD
D5h,imm8

AL = AL+AH*imm8
AH = 0

Byte DIVision:
DIVB imm8
D4h,0Ah => AAM
D4h,imm8

AL = MOD AL/imm8
AH = AL/imm8

can generate a divide by 0 exeption.

can it be interesting to add theses mnemonics by ourselves and don't care about intel decision?
Post 12 Feb 2011, 18:01
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revolution
When all else fails, read the source


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revolution
Code:
mulb equ aad
divb equ aam    
Done.
Post 12 Feb 2011, 18:18
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edfed



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edfed
none.
Code:
mulb equ byte 0D4h
divb equ byte 0D5h

aad equ mulb,10
aam equ divb,10
    


something like this, because AAM and AAD are composed by the opcode 0D4h/0D5h followed by immediate value 10
Post 12 Feb 2011, 18:44
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revolution
When all else fails, read the source


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revolution
Did you try it? It works:
Code:
mulb equ aad
divb equ aam

mulb 5
divb 34    
Post 12 Feb 2011, 18:59
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edfed



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edfed
cool, then, no more need for this mnemonic operation.
i suggested it just because some reading about instruction set pointed me this fact.
Post 12 Feb 2011, 19:13
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ouadji



Joined: 24 Dec 2008
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ouadji

bscc brcc bccc (bit set/reset/complement if conditions)
Code:
bsnz eax,12    


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Post 12 Feb 2011, 19:40
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revolution
When all else fails, read the source


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revolution
ouadji wrote:
bscc brcc bccc (bit set/reset/complement if conditions)
Code:
bsnz eax,12    
What is the binary encoding for that?
Post 12 Feb 2011, 19:42
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ouadji



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ouadji

I am a programmer not a microprocessor designer.

and also the semiconductors implantation ?

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Post 12 Feb 2011, 19:47
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revolution
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revolution
ouadji wrote:
I am a programmer not a microprocessor designer.
So how do you expect fasm to make that opcode work?

edfed was suggesting an alternate mnemonic for an existing opcode, which is easily doable with fasm. You appear to be suggesting completely new opcodes that the CPU doesn't have.
Post 13 Feb 2011, 01:38
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ouadji



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ouadji
Quote:
You appear to be suggesting completely new opcodes that the CPU doesn't have.
yes

i see no need and no utility to create an alternate mnemonic for an opcode that already exists.

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Post 13 Feb 2011, 10:56
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revolution
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ouadji wrote:
i see no need and no utility to create an alternate mnemonic for an opcode that already exists.
NOP == XCHG (e)AX,(e)AX
Post 13 Feb 2011, 12:10
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ouadji



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ouadji

the exception that proves the rule ? Wink
hummm ... another one ?

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Post 13 Feb 2011, 16:39
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revolution
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revolution
JA == JNBE

There are more. Lots more.
Post 13 Feb 2011, 16:50
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edfed



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edfed
retn = ret
Post 13 Feb 2011, 18:10
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