flat assembler
Message board for the users of flat assembler.
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revolution
Code: mulb equ aad divb equ aam |
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edfed
none.
Code: mulb equ byte 0D4h divb equ byte 0D5h aad equ mulb,10 aam equ divb,10 something like this, because AAM and AAD are composed by the opcode 0D4h/0D5h followed by immediate value 10 |
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revolution
Did you try it? It works:
Code: mulb equ aad divb equ aam mulb 5 divb 34 |
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edfed
cool, then, no more need for this mnemonic operation.
i suggested it just because some reading about instruction set pointed me this fact. |
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ouadji
bscc brcc bccc (bit set/reset/complement if conditions) Code: bsnz eax,12 |
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revolution
ouadji wrote: bscc brcc bccc (bit set/reset/complement if conditions) |
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ouadji
I am a programmer not a microprocessor designer. and also the semiconductors implantation ? |
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revolution
ouadji wrote: I am a programmer not a microprocessor designer. edfed was suggesting an alternate mnemonic for an existing opcode, which is easily doable with fasm. You appear to be suggesting completely new opcodes that the CPU doesn't have. |
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ouadji
Quote: You appear to be suggesting completely new opcodes that the CPU doesn't have. i see no need and no utility to create an alternate mnemonic for an opcode that already exists. |
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revolution
ouadji wrote: i see no need and no utility to create an alternate mnemonic for an opcode that already exists. |
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ouadji
the exception that proves the rule ? ![]() hummm ... another one ? |
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revolution
JA == JNBE
There are more. Lots more. |
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edfed
retn = ret
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