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Index > Main > Super-secret debug capabilities of AMD processors !

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killasmurf86



Joined: 29 Sep 2010
Posts: 36
killasmurf86 16 Nov 2010, 18:11
You probably, have read already this by now, but here I go:

http://www.woodmann.com/collaborative/knowledge/index.php/Super-secret_debug_capabilities_of_AMD_processors_!

Sounds interesting


Last edited by killasmurf86 on 16 Nov 2010, 18:23; edited 2 times in total
Post 16 Nov 2010, 18:11
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mindcooler



Joined: 01 Dec 2009
Posts: 423
Location: Västerås, Sweden
mindcooler 16 Nov 2010, 18:33
Useful for what?
Post 16 Nov 2010, 18:33
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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid 16 Nov 2010, 23:52
Moved to main, fixed link, and removed link-related posts. Not sure what mindcooler's post was about, so I left it here
Post 16 Nov 2010, 23:52
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f0dder



Joined: 19 Feb 2004
Posts: 3175
Location: Denmark
f0dder 18 Nov 2010, 09:10
mindcooler wrote:
Useful for what?
Much faster tracing engines, since you let the hardware handle checks before invoking the software handler.

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Post 18 Nov 2010, 09:10
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Czerno



Joined: 02 Jun 2009
Posts: 8
Czerno 20 Nov 2010, 10:38
Hello! I'm delighted my little findings aroused some interest...

As this is not strictly speaking FASM related, I wouldn't have posted here; since others have though, let me throw a call for action to this fine community... Help needed !

If you own a CPU from AMD and know how to use a kernel-mode debugger - even Debug will do if you know what you're doing, preferably the FreeDOS version - please check and report availability of the "secret" MSRs and expanded debugging functions. I want results correlated with AMD processor generation (all I have is an old K7). Newer processors may not need a "password", do check that too.

Verify :
- Instruction execution breakpoints with address mask
- I/O port access BPs with address mask and data mask, and reversing the condition (break on NON-match).
- Memory data BPs on write, resp. read/write, with address and or data masking : this is problematic at the moment. Does it actually work, does it depend on processor generation/revision ?

Everything has to be combined with the settings of the Control register (MSR C001_1024). Check my writing at Woodman's collaborative library (URL was provided by killasmurf86 at the beginning of this thread), but heed the warning that it is not up to date and has errors in it...

We also want this tested in 64 bit mode ( my proc doesn't have AMD64).


Revelation time is over, ;now is time for (tedious) combinatorial testing

If Tomasz doesn't care, this thread could hold reports of reults.
In addition/alternatively, you may email me with your findings.

What is already known to be working is nice, ripping that apart altogether will be fun, and open fantastic opportunities.

Cheers,

--
Czernobyl
Post 20 Nov 2010, 10:38
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