If i want to use any usb hardware, i have to map some of its registers and possibly memory into physical address space.

- what component is responsible for that?
- will usb device get predetermined address mapping? meaning that manufacturers must know what addresses are used by others to avoid conflict?
- or usb bus has predetermined memory range wich is asigned randomly to each device?







is it same for pci/ata/sata/firewire/lpt/com?
and pci-e/agp?

USB is not really a bus at all, it is really an external inerface driven by an internal host controller. Should be called USI

The USB host controllers are usually implemented as devices on the PCI bus. They can be accessed via INT 1Ah / AX=0B103h . There are at least 3 different types of USB hosts - UHCI, OHCI and EHCI which must be specified with ECX = 0C0300h (UHCI), 0C0310h (OHCI) or 0C0320h (EHCI). Check out Ralf Brown's interrupt list for full details.

good to know, thx.

but my question remains open.

does individual device claim address space/irq, or bus has it reverved, and then assign it to devices.

You better check here, but AFAIK there will be only one IRQ assigned to the USB controller and then you'll know what device requested attention by looking some device ID in the packet.

The host controller can be programmed directly, or the southbridge when the host is integrated into the chipset. There is usually a default USB setup, and the BIOS does some configuring. Buffers are established for data transfer, interrupts (APIC, x2APIC) are fired to signal state changes.

Read about ACPI for a general way to setup hardware, or program specific drivers for each supported device. Of course, the BIOS could be used as revo1ution suggests. Given the 64-bit address space it becomes easy to memory-map all hardware --- just like back in the good old days.

We should also remember that in the X86 architecture the CPU has an I/O address space as well as memory address space. Both operate at the full CPU address/data bus speeds and are selected via the IO/-M control pin. IN and OUT instructions access the I/O address space and assert the IO pin. So "memory mapping" doesn't have to fragment the memory address space like it does in Motorola architectures. (Not that I'm trying to say Intel has designed the perfect CPU - far from it! )

The PCI bus devices, including USB host controllers, appear in the I/O address space, and can also be accessed via the PCI configuration space. You might need to read up on the PCI specs as well.

BTW, AFAIK the I/O address space is still limited to 16 bits, meaning 65536 max I/O addresses. Is this true?

revo1ution,

We should also remember that we rarely encounter ISA bus nowaday. PCI has commands, not dedicated pins, to distinguish I/O port and memory access.

I/O address space is limited to 65536 ports, that's right.

The CPU hardware design as I have described cannot be replaced by peripheral devices connected to it AFAIK, I/O ports are still implemented by toggling the IO/-M pin on the CPU, in "parallel" with the memory address bus for the first 64K, but this has nothing whatever to do with the ISA bus per se Of course the PCI bus also must work with the native CPU, unless it creates some new special operating mode?

While what you say is correct about the speed of the external bus interaction, there is a very large difference in how the CPU will process I/O and memory instructions.

Memory instructions can go through the cache hierarchy and be overlapped with other transfers, they can even be reordered, if the MTRR settings allow it.

But the I/O accesses do not use the cache and the entire CPU is prevented from progressing until the transfer is complete. I/O operations cannot be overlapped and cannot be reordered. They are considerably slower.

It is the north and south bridge which have the special operating mode. Memory access in the PCI configuration space is routed to the proper destination - reducing (eliminating?) the need for port I/O.

Off topic stuff moved to here