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revolution 22 Jun 2010, 10:00
Read:
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1 CHAPTER 18 ARCHITECTURE COMPATIBILITY |
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22 Jun 2010, 10:00 |
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ouadji 22 Jun 2010, 10:34
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22 Jun 2010, 10:34 |
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b1528932 22 Jun 2010, 11:24
no information about 0x66 prefix.
how do i know if i can use it? |
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22 Jun 2010, 11:24 |
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ouadji 22 Jun 2010, 11:38
Intel® 64 and IA-32 Architectures Optimization Reference Manual
3.4.2.3 Length-Changing Prefixes (LCP) The length of an instruction can be up to 15 bytes in length. Some prefixes can dynamically change the length of an instruction that the decoder must recognize. Typically, the pre-decode unit will estimate the length of an instruction in the byte stream assuming the absence of LCP. When the predecoder encounters an LCP in the fetch line, it must use a slower length decoding algorithm. With the slower length decoding algorithm, the predecoder decodes the fetch in 6 cycles, instead of the usual 1 cycle. Normal queuing throughout of the machine pipeline generally cannot hide LCP penalties. The prefixes that can dynamically change the length of a instruction include: • operand size prefix (0x66) • address size prefix (0x67) http://www.intel.com/Assets/PDF/manual/248966.pdf also : 2.1.2.2 Instruction Fetch Unit / Instruction PreDecode all processors based on x86 architecture are be able to do that. all cpu based on x86 architecture are be able to enter protected mode too ... (all cpu since 80286) |
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22 Jun 2010, 11:38 |
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b1528932 22 Jun 2010, 21:22
Quote: all processors based on x86 architecture are be able to do that. so when i start executing my bootloader the first thing i should do is testing for cpuid in eflags.id? can i assume that i have access to upper 16 bits of eflags, and consequently being 32bit address aware? |
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22 Jun 2010, 21:22 |
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baldr 22 Jun 2010, 21:52
b1528932,
Probably you can safely assume 386+ CPU, or check and say "Upgrade your box, or press any key if you're brave enough." cpuid is Pentium+/later 486 feature. |
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22 Jun 2010, 21:52 |
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bitshifter 23 Jun 2010, 04:01
This was in the old Wofenstein3D sources
Code: PROC _CheckIs386 PUBLIC _CheckIs386 pushf ; Save flag registers, we use them here xor ax,ax ; Clear AX and... push ax ; ...push it onto the stack popf ; Pop 0 into flag registers (all bits to 0), pushf ; attempting to set bits 12-15 of flags to 0's pop ax ; Recover the save flags and ax,08000h ; If bits 12-15 of flags are set to cmp ax,08000h ; zero then it's 8088/86 or 80188/186 jz not386 mov ax,07000h ; Try to set flag bits 12-14 to 1's push ax ; Push the test value onto the stack popf ; Pop it into the flag register pushf ; Push it back onto the stack pop ax ; Pop it into AX for check and ax,07000h ; if bits 12-14 are cleared then jz not386 ; the chip is an 80286 mov ax,1 ; We now assume it's a 80386 or better popf retf not386: xor ax,ax popf retf ENDP Its in TASM IDEAL syntax! |
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23 Jun 2010, 04:01 |
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Tyler 11 Jul 2010, 01:06
HelpPC, Misc -> CPU topic wrote:
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11 Jul 2010, 01:06 |
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