ok, I think i understand the theory around VBE (bank, window, etc). But my problem is how to put that all in the code. Remembering i'm in PM.

All video cards/chips are different.

There are some pseudo-standards among all cards but it is not guaranteed.

There is no shortcut here, you have to know what your card does internally.

the theory around VBE (bank, window, etc). But my problem is how to put that all in the code. Remembering i'm in PM.

what is better, and why: make a boot file only to load the kernel and into kernel set up A20, PM, etc. or to put that all into boot file?

Will the boot sector keep in memory after the boot?

    cli
    lgdt [gdtr]
    mov eax,cr0
    or  al, 1            ; enable PE flag (bit 0) in CR0
    mov cr0, eax    

    jmp 8:@f
@@:
use32
    jmp 8000h            ; go to kernel

      align 8
gdtr: dw 23,gdtr-3
      db 0
      dw 0FFFFh,0,9A00h,0CFh
      dw 0FFFFh,0,9200h,0CFh    

gdtr: dw 23,gdtr-3
      db 0
      dw 0FFFFh,0,9A00h,0CFh
      dw 0FFFFh,0,9200h,0CFh    

2. what does the align 8 do? ok, it align 8 bits, but what that mean!?

3. The worse step:

Code:

gdtr: dw 23,gdtr-3
      db 0
      dw 0FFFFh,0,9A00h,0CFh
      dw 0FFFFh,0,9200h,0CFh    

GEeeeeezzzzzz what they meannnnnnn

The trick with pseudo-descriptor is to put it into unused GDT[0] entry (and gdtr-3 is due to difference between their sizes: 16-bit pseudo-descriptor is 5 bytes long, GDT entry — 8).

With such arrangement, align 8 makes GDT entries unaligned (they're at 8*n+5).

        ; GDT Selector Rings
        GDT_RPL_RING0                                   equ 0x0000
        GDT_RPL_RING1                                   equ 0x0001
        GDT_RPL_RING2                                   equ 0x0002
        GDT_RPL_RING3                                   equ 0x0003
        GDT_RPL_MASK                                    equ 0x0003

        ; GDTENTRY.Access
        GDT_PRESENT                                     equ 0x80

        GDT_RING0                                       equ 0x00
        GDT_RING1                                       equ 0x20
        GDT_RING2                                       equ 0x40
        GDT_RING3                                       equ 0x60

        GDT_CODE                                        equ 0x10
        GDT_CODE_EXECUTE                                equ 0x08
        GDT_CODE_READ                                   equ 0x02

        GDT_DATA                                        equ 0x10
        GDT_DATA_WRITE                                  equ 0x02
        GDT_DATA_READ                                   equ 0x00

        GDT_STACK                                       equ 0x10
        GDT_STACK_WRITE                                 equ 0x02
        GDT_STACK_READ                                  equ 0x00
        GDT_STACK_EXPANDDOWN                            equ 0x04
        GDT_STACK_EXPANDUP                              equ 0x00

        GDT_SYSTEM                                      equ 0x00

        ; GDTENTRY.Flags
        GDT_GRANULARITY_BYTES                           equ 0x00
        GDT_GRANULARITY_PAGES                           equ 0x80

        GDT_16BIT                                       equ 0x00
        GDT_32BIT                                       equ 0x40
        GDT_64BIT                                       equ 0x20
        GDT_USER                                        equ 0x10


        GDT_ACCESS_MASK                                 equ (GDT_PRESENT or GDT_RING3 or GDT_DATA or GDT_CODE_EXECUTE or GDT_STACK_EXPANDDOWN or GDT_DATA_WRITE)
        GDT_FLAGS_MASK                                  equ (GDT_GRANULARITY_PAGES or GDT_32BIT or GDT_64BIT or GDT_USER)
        GDT_LIMITHI_MASK                                equ 0x0F


        struc GDTENTRY b,l,f,a
         {
                .LimitLo        dw (l and 0xFFFF)
                .BaseLo         dw (b and 0xFFFF)
                .BaseMi         db ((b shr 16) and 0xFF)
                .Access         db (a and GDT_ACCESS_MASK)
                .Flags_LimitHi  db ((f and GDT_FLAGS_MASK) or ((l shr 16) and GDT_LIMITHI_MASK))
                .BaseHi         db (b shr 24)
         }

        struc GDTR32ENTRY b,e
         {
                .Size           dw (e - b - 1)
                .Address        dd (b)
         }
              

  gdtr32  GDTR32ENTRY gdt32.start,gdt32.end 

      align 8 ; important lower 3 bits are used for RPL

       gdt32: 
 .start: ;        base       limit      flag access 
     .null   GDTENTRY 0x00000000,0x00000000,0x00,0x00 
   .data   GDTENTRY 0x00000000,0x000FFFFF,(GDT_GRANULARITY_PAGES or GDT_32BIT),(GDT_PRESENT or GDT_RING0 or GDT_DATA or GDT_DATA_READ or GDT_DATA_WRITE) 
      .code   GDTENTRY 0x00000000,0x000FFFFF,(GDT_GRANULARITY_PAGES or GDT_32BIT),(GDT_PRESENT or GDT_RING0 or GDT_CODE or GDT_CODE_READ or GDT_CODE_EXECUTE) 
    .code64 GDTENTRY 0x00000000,0x000FFFFF,(GDT_GRANULARITY_PAGES or GDT_64BIT),(GDT_PRESENT or GDT_RING0 or GDT_CODE or GDT_CODE_READ or GDT_CODE_EXECUTE) 
    .stack  GDTENTRY 0x00000000,0x000FFFFF,(GDT_GRANULARITY_PAGES or GDT_32BIT),(GDT_PRESENT or GDT_RING0 or GDT_STACK or GDT_STACK_READ or GDT_STACK_WRITE or GDT_STACK_EXPANDUP) 
     .end:    

        cli

     lgdt [gdtr32]

   mov eax,cr0
 or eax,1;CPU_CR0_PE
 mov cr0,eax 

    jmp pword ((gdt32.code - gdt32.start) or GDT_RPL_RING0):pmode
;                   ^this is the GDT offset^    ^set priv lvl^  ^code location
align 4
use32
pmode:     

Saving 11 bytes is a matter of life and death, eh? This is a completely twisted and rather useless "trick". And it's definitely not the best way for a beginner to understand the already twisted Intel arch structures.

Of course. In this case it's missing a dw...

struc descriptor [def] {
common
  local .base,.limit,.type
  .base = 0
  .type = 0x0010; defaults: byte-granularity 16-bit not-present DPL0 read-only not-accessed data
forward
  match =base==v, def \{ .base = v \}
  match =limit==v, def \{
    \local matched
    matched equ 0
    match vv*=4k,v \\{
      .limit = vv
      .type = .type or 0x8000
      restore matched
      matched equ 1
    \\}
    match =0, matched \\{
      .limit = v
    \\}
    restore matched
  \}
  match =a, def \{ .type = .type or 1 \}
  match =w, def \{ .type = .type or 2 \}
  match =e, def \{ .type = .type or 4 \}
  match =code, def \{ .type = .type or 8 \}
  match =r, def \{ .type = .type or 2 \}
  match =c, def \{ .type = .type or 4 \}
  match =dpl==.dpl, def \{ .type = .type and not 0x0060 or ((.dpl) and 3) shl 5 \}
  match =p, def \{ .type = .type or 0x80 \}
  match =avl==.avl, def \{ .type = .type and not 0x0100 or ((.avl) and 1) shl 12 \}
  match =64bit, def \{ .type = .type or 0x2000 \}
  match =32bit, def \{ .type = .type or 0x4000 \}
common
  if .type and 0x6008 = 0x6008
    display "Reserved combination of L and D bits in code segment descriptor", 13, 10
    err
  end if
  dw    .limit and 0xFFFF
  dw    .base and 0xFFFF
  db    .base shr 16 and 0xFF
  db    .type and 0xFF
  db    (.type shr 8 and 0xF0) or (.limit shr 16 and 0x0F)
  db    .base shr 24 and 0xFF
}

macro descriptor [def] {
common
  local .
  . descriptor def
}    

align 8
gdt     dq  0
code0_selector = $-gdt
code3_selector = code0_selector+3
        descriptor code, 32bit, dpl=3, base=0, limit=0xFFFFFF*4k, p, r
data0_selector = $-gdt
data3_selector = data0_selector+3
        descriptor data, 32bit, dpl=3, base=0, limit=0xFFFFFF*4k, p, w    

If you want to run 32 bit user programs, add another data and code entry with GDT_RING3 instead and then use jmp/iret to switch into user mode (interrupts/syscalls will later let you back to ring 0).

The 16 bit IDT…

align 8
dw 0
gdtr:
dw gdtsize
dd gdtbase
    

lgdt [gdtr]
    

Do you realise already that after you've switched CPU into PM, most of RM services are unavailable? There are VBE/PCIBIOS/PnP 32-bit interfaces, but you must implement keyboard/FDD/HDD access by yourself (or switch back to RM).