flat assembler
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> OS Construction > Paging and Specific Locations in Memory |
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revolution 29 Apr 2010, 03:27
The graphics controller only ever sees physical memory addresses. The paging MMU is buried deep inside the CPU and external devices can't see it.
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29 Apr 2010, 03:27 |
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Tyler 29 Apr 2010, 03:59
Thanks revolution. I didn't think of descriptor tables in my original post, are their positions affected automatically after I enable paging, or do I have to reload their locations?
For example, I have GDTR(the actual register, not the common label name) pointed at 0x100, but I have 0x100 mapped as 0x1000, does GDTR now point to 0x1000, or must I reload it with the location mapped to 0x100? Are tables affected at all by paging? All the locations used are just theoretical. |
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29 Apr 2010, 03:59 |
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revolution 29 Apr 2010, 04:08
Tyler: Did you download the Intel/AMD documents I suggested? Read the Intel manual volume 3A, chapter 3: "PROTECTED-MODE MEMORY MANAGEMENT". You can find all the gory details of exactly how it works. With pictures and diagrams and things also.
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29 Apr 2010, 04:08 |
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Tyler 29 Apr 2010, 04:20
It wasn't working when I checked last night, it is today though.
Last night, I clicked on the support page link, it stalled until my connection timed out multiple times, but it's good now. |
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29 Apr 2010, 04:20 |
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edfed 29 Apr 2010, 07:21
GDTR point to linear memory.
TR points to descriptor in GDT as a segment registers (because it is a segment). etc... you have the chance to speak and read english, down the manuals and read them. |
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29 Apr 2010, 07:21 |
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vid 29 Apr 2010, 10:47
Paging-wise, virtual B8000 remainst mapped to physical B8000. But the northbridge sends accesses to it to Video RAM, instead of regular RAM. This is set by VGA and chipset register.
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29 Apr 2010, 10:47 |
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