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Index > OS Construction > paging and addreses > 6b

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a115433



Joined: 05 Mar 2010
Posts: 144
a115433
i know of 3 paging systems.
32bit can support up to 4 gigs, with pse36 up to 64 gigs with 4mega pages.
pae can support 64 bibs
ia32e can support 48 bits.


what about address spaces > 48 bits?
what paging model is used then?
or maybe they will do something like PSE, and if pdpte in ia32e paging will contain this bit, it would point to 'extended' PDE?
Post 17 Mar 2010, 18:51
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chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
well,.....
at the moment there is just am implementation of 48 bit virtual address space mapped to 52 bit physical addresses from AMD.
and Intel has also a maximum of 48 bit virtual adress space. (and i think also a maximum of 52 bit pysical ram.)
the address has to be in canonical adress form. that means, that bit Nr 48 is the sign extended bit.
(bits 49 to 64 hast to be the same like bit 48.)

but in the machine spefific registers you can read how many bits are usable in virtual and physical memory.
Post 17 Mar 2010, 21:22
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Feryno



Joined: 23 Mar 2005
Posts: 454
Location: Czech republic, Slovak republic
Feryno
52 bits of physical memory is architectural limit of AMD64/Intel IA32e, if you try to determine the phys mem limit at current CPUs using the CPUID instruction, you will get much less value (36 bits in worst case - my CPU, 40 bits if you have a luck)
virtual memory is in canonical form when bit 47. is the same as all bits 63-48
so canonical virt. mem is in range:
0000000000000000 - 00007FFFFFFFFFFF
FFFF800000000000 - FFFFFFFFFFFFFFFF
the lowest bit counts from 0 so the 48th bit is bit 47. - that caused some problems to microsoft kernel developper(s), I posted it here:
http://board.flatassembler.net/topic.php?t=11319
the correct formula to validate canonical virt. mem is:
Code:
; rax = virt. mem
sar rax,47
inc rax
cmp rax,1
jbe canonical    
Post 18 Mar 2010, 08:36
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a115433



Joined: 05 Mar 2010
Posts: 144
a115433
so virtual memory is always 48 bit, higher wouldnt work under pml4
and physical is 52?
Post 18 Mar 2010, 13:12
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baldr



Joined: 19 Mar 2008
Posts: 1651
baldr
a115433,

You don't have to guess or assume, there is cpuid (with eax==0x80000008, since P4HT). PML4 part of linear/virtual address can be extended from 9 bits in IA-32e to 25 bits easily (I doubt it, though).
Post 18 Mar 2010, 15:18
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Alphonso



Joined: 16 Jan 2007
Posts: 294
Alphonso
I thought that the physical address limit of 32-bit PAE was the same as 64-bit and the 64GiB limit came from the older 32-bit processors that had 36 address lines. Disregarding the practicality of it, let me know if I've got it wrong.
Post 18 Mar 2010, 15:34
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baldr



Joined: 19 Mar 2008
Posts: 1651
baldr
Alphonso,

Good old IA-32 processors had 14+32=46 bit logical address space, yet unused since flat model prevails. It's up to a programmer.
Post 18 Mar 2010, 16:49
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a115433



Joined: 05 Mar 2010
Posts: 144
a115433
how you address 46 bit?
unreal mode with base > 0?
i think it wont work, because cpu will check access no matter what mode ur in ;/
Post 18 Mar 2010, 17:45
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