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a115433



Joined: 05 Mar 2010
Posts: 144
a115433
it is possible to update a bios. i never did that, but i saw many tutorials.
also bios data is writeable - you can change bios settings.

is it possible to damage bios by overwriting its code?
are there some security measures to prevent accidential or intentional writing to bios area?

do you have any experience in this?


when cpu starts, first instruction is fetched from bios. bios code is responsible for mapping devices into memory and port address.
how does eeprom exist in mapped space, before something mapped it?
Post 08 Mar 2010, 20:12
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ouadji



Joined: 24 Dec 2008
Posts: 1081
Location: Belgium
ouadji

Quote:

how does eeprom exist in mapped space, before something mapped it?
the processor begins execution at FFFF_FFF0H. (eprom)
The first bios opcode is at this address. (real mode)
First opcode ... the concept of mapping does not exist yet. (only linear physical address)
To access the mapping feature (page table-cr3) ,
the processor must first go into protected mode (cr0)
RAM is placed at the bottom of the address space
because the initial DS after reset is 0.
Quote:

a) it is possible to update a bios
b) is it possible to damage bios by overwriting its code
a) yes.
b) yes, obviously.

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Post 08 Mar 2010, 21:06
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a115433



Joined: 05 Mar 2010
Posts: 144
a115433
To access the mapping feature (page table-cr3) ,
mapping as in mapping hardware to linear address space, and mapping hardware to port io address space.

i though eeprom is read only, and can be written only by special radiation or something. how bios update is performed then? is it reversable? is it safe to do that on real machine?
Post 08 Mar 2010, 21:46
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
I think it might be interesting for you this site: http://sites.google.com/site/pinczakko/home

About the mapping, I think there is some misunderstanding here, mapping memory with page tables is not a mandatory way to access hardware, its only purpose would be simply to add ab address translation layer to get the linear address.

The hardware already listen to some memory address ranges, some other hardware requires previous programming to start listening (PCI devs for instance), but in any case, the processor is completely ignorant about that fact*, it simple read/write to a given memory address and it is the responsibility of the supporting hardware to route the operation.

*AMD64 includes a memory controller and I think Intel started to do the same, but in any case it has nothing to do with CR3 nor CR0.

PS: Forgot to tell, updating BIOS is not as simple as writing to F0000-FFFFF memory range (which is also insufficient by the current BIOS sizes), motherboard specific procedures has to be taken to write to the EEPROM memory. But, as you can see in the site's references, you can still do custom updates by using the utilities provided for your motherboard.
Post 08 Mar 2010, 22:05
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ouadji



Joined: 24 Dec 2008
Posts: 1081
Location: Belgium
ouadji

The mapping does not exist before protected mode.
Before the protected mode, exist only linear physical addressing.
Before the protected mode, the concept of mapping has no meaning
First access to hardware is done in real mode and physical addressing.
The BIOS knows the physical address of the basic hardware components.
(don't forget that bios is manufactured by the manufacturer of the motherboard)
Quote:

is it safe to do that on real machine?

there is always a risk. Updating the bios is not without risk.
If it fails, then the machine has no bios, and is unusable.
If there are no problems, it's not necessary to update the BIOS.
Don't do it just for fun.

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Post 08 Mar 2010, 22:10
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Quote:
Before the protected mode, the concept of mapping has no meaning
From CPU perspective, it still has lots of sense for the memory controller for instance.


BIOS and Kernel Developer's Guide for AMD AthlonTM 64 and AMD OpteronTM Processors wrote:
3.4.5 Memory-Mapped I/O Address Map Registers
These registers define sections of the memory address map for which accesses should be routed to
memory-mapped I/O. MMIO regions must not overlap each other. For addresses within the specified
range of a base/limit pair, requests are routed to the noncoherent HyperTransport link specified by the
destination Node ID and destination Link ID.
Addresses are considered to be within the defined range if they are greater than or equal to the base
and less than or equal to the limit. For the purposes of this comparison, the lower unspecified bits of
the base are assumed to be 0s and the lower unspecified bits of the limit are assumed to be 1s.
An address that maps to both DRAM and memory-mapped I/O is routed to MMIO.
Programming of the MMIO address maps must be consistent with the Top Of Memory and Memory
Type Range registers (see Chapter 13, “Processor Configuration Registers”). In particular, accesses
from the CPU can only hit in the MMIO address maps if the corresponding CPU memory type is of
type IO. For accesses from I/O devices, the lookup is based on address only.
Post 08 Mar 2010, 22:29
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ouadji



Joined: 24 Dec 2008
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ouadji

From CPU perspective ... the "mapping" from hardware perspective ...
I was talking more from OS perspective.
To me, this is not the real meaning of this word, but hey, I agree.
But I keep what I said, more in line, I think, with the true concept of mapping.

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Post 08 Mar 2010, 22:45
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