Message board for the users of flat assembler.
> Main > Please, help with SSE5 opcode encoding
I am not fully deep inside SSE5, i have no time to study the DREX
byte for 0F 24 / 0F 25, and i cannot encode it manually, at the moment
(if i do not mistake, fasm will support them in 1.70)
Have you sample of dumped bytecode for SSE5 to read, especially for
According to AMD,
0F25 - OPCODE - MODRM - SIB - DREX -DISP1/2/4 - IMM8
it is to say, my question :
apart from the MODRM, are there other modification to the above instruction len ? (probably NOT)
It is to say, does the DREX byte to modifies/allows more immediates bytes or displacements in the istruction? (probably NOT)
Thanxs in advance,
EDIT: forgotten 32bit possibly
|14 Jan 2010, 02:43||
DREX merely replaces REX prefix, allows to declare one more XMM register and contains one of two operand configuration bits. So the answer is not and not.
EDIT: mod, move this topic to Main please
|14 Jan 2010, 10:10||
< Last Thread | Next Thread >
Copyright © 1999-2020, Tomasz Grysztar. Also on YouTube, Twitter.
Website powered by rwasa.