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Madis731



Joined: 25 Sep 2003
Posts: 2141
Location: Estonia
Madis731
Hi,
I've been searching for an easy to use Logical circuit simulator. Because I could not find one, I started this thread and now I've found one:

http://ozark.hendrix.edu/~burch/logisim/

One executable, no installation, updated recently. The only bad thing is that it requires Java, but most of us have it anyway (for OpenOffice or some web applications).

I tried making one CPU from scratch and I don't get the problem around "It is hard to make a CPU" jada-jada Razz

There's even a single-cycle CPU described here:
http://cis.k.hosei.ac.jp/~yamin/lectures/organization/single-cycle.html

If I ever get to it, I will try to make a TTA CPU (http://en.wikipedia.org/wiki/Transport_triggered_architecture), and a picture here: http://en.wikipedia.org/wiki/File:Transport_Triggered_Architecture.png


Description: My sample CPU project with ROM
Download
Filename: LogiSim.7z
Filesize: 3.05 KB
Downloaded: 167 Time(s)


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My updated idol Very Happy http://www.agner.org/optimize/
Post 22 Dec 2009, 12:42
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
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revolution
I once designed an FPGA Asynchronous CPU. It even worked, surprisingly. It was of no practical use, but was very interesting to design.

ARM also made some. But I guess they also found them to be of no practical use.
Post 22 Dec 2009, 12:58
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Madis731



Joined: 25 Sep 2003
Posts: 2141
Location: Estonia
Madis731
I'm browsing through the http://www.opencores.org/ site and there seems to be a lot going on with open-source CPUs. this one caught my eye Smile - its a GPU
I love the description on one of the designs (http://www.opencores.org/project,cpu8080): "This is an 8080 core I created as a project to get to know Verilog. "

EDIT: I guess asynchronous CPU wouldn't be commercially viable. When a manufacturers tells you that it doesn't have a clock, they can't sell you one. Instead someone (company #2) will say "we have 1THz CPU" and everyone rushes to the shops.

@revolution: do you have any hints on free-Windows-VHDL/Verilog-IDE/synthesizers? Smile Xilinx is 30-day trial and 5GB Sad & 100000+ files. I'm still trying to start with SynaptiCAD.
Post 22 Dec 2009, 13:35
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
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Location: In your JS exploiting you and your system
revolution
Madis731 wrote:
@revolution: do you have any hints on free-Windows-VHDL/Verilog-IDE/synthesizers? Smile Xilinx is 30-day trial and 5GB Sad & 100000+ files. I'm still trying to start with SynaptiCAD.
Xilinx have a free version also. But of course it is limited. I only used it because they bought the old Philips "CoolRunner" technology and I had existing designs that needed to be upgraded.

But I have always liked the Altera Baseline software. Really easy to use, but of course only supports the Altera hardware.

Other than that I've not used any free design programs. All the ones I use now are paid versions.
Post 22 Dec 2009, 14:20
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shoorick



Joined: 25 Feb 2005
Posts: 1605
Location: Ukraine
shoorick
i have some of soviet 8080 clones Smile i could send it free of charge, but after sending empty PCB to Russia i would not like to visit post with such kind of message Very Happy hardware cpu may run some time faster then same emulated on the same clock speed Smile
Post 22 Dec 2009, 14:49
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TmX



Joined: 02 Mar 2006
Posts: 821
Location: Jakarta, Indonesia
TmX
Madis731 wrote:

@revolution: do you have any hints on free-Windows-VHDL/Verilog-IDE/synthesizers? Smile Xilinx is 30-day trial and 5GB Sad & 100000+ files. I'm still trying to start with SynaptiCAD.


Hi Madis,

I once learned VHDL, using ISE WebPack. It's free.
Post 22 Dec 2009, 17:17
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Here I found an asynchronous open source processor: http://www.ics.forth.gr/carv/async/demo/

Unfortunately the download is broken Sad
Post 23 Dec 2009, 16:35
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sleepsleep



Joined: 05 Oct 2006
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sleepsleep
i sometime wonder than if we could use some simple, yet abundance unwanted rubbish to build a really simple cpu that maybe 1 hz or 0.5 hz?
maybe using drops or water to ...hmmm.
Something like more mechanical cpu? Idk,but i think it is kinda cool and athentic to have a mechanical stuff that dont need electricity but can count :p
Post 24 Dec 2009, 12:22
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Madis731



Joined: 25 Sep 2003
Posts: 2141
Location: Estonia
Madis731
@sleepsleep: with water and pipes you can make an analog computer, but that's a whole different story and categories of problems.
http://en.wikipedia.org/wiki/Analog_Computer

Using water to run some pistons/valves/etc. or some pneumatic system may be really slow unless done on a microscopic level.
Post 24 Dec 2009, 12:33
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tom tobias



Joined: 09 Sep 2003
Posts: 1320
Location: usa
tom tobias
sleepsleep wrote:
... i think it is kinda cool and athentic to have a mechanical stuff that dont need electricity but can count....

sundials
Eratosthenes computes the circumference of the earth using two sticks
Big sticks
Tesla's kinetic radiant energy
all, accomplished prior to advent of desktop computers, internet, telephones, etc....

Smile
Post 24 Dec 2009, 12:39
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DustWolf



Joined: 26 Jan 2006
Posts: 373
Location: Ljubljana, Slovenia
DustWolf
Madis731 wrote:
I tried making one CPU from scratch and I don't get the problem around "It is hard to make a CPU" jada-jada Razz


Is that even something people really say BTW?

I once drew a functioning 1-bit-register CPU in Electronics WorkBench (been a few years back, I'll look for the file...). It wasn't hard, but if you ask those people who believe the only way to make an OS is to write up another Linux, and the only way to make a CPU is to make another x86, then yes, it's a nightmare.

When thinking about how to make something feasible in the real world, you turn to the PC architecture derivates and quickly find out that it's a total mess scrapped together in a way that happens to work and has nothing in common with optimization, that's got to take make you feel the hopelessness of modern computer performance. In other words, you could make an add-in card that helps the computer process data much faster, but you couldn't interface it in such a way that it would actually improve performance.

The only thing I can actually think of that may still work is having a FPGA card that lets you install new hardware asif it were software: completely freely.

LP,
Jure
Post 24 Dec 2009, 23:27
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Madis731



Joined: 25 Sep 2003
Posts: 2141
Location: Estonia
Madis731
I think there is a problem when designing an instruction set for a CPU. What to x86 is important, is optimizing some instructions to use fewer bytes and let other (less important) instructions encode in as much as 15 bytes.

I have studied ARM and I tend to agree with their philosophy more. What you do is set some instruction width (say 128 bits) and resolve many problems:
1) No alignment problems
2) You know where to look the next instruction
* this means many parallel units can decode and execute instructions
3) There are no size-optimization issues

Of course you can't use tricks that are used on most 256b.com site demos, but then - do we need them? The performance we gain with fixed size instruction length is making the (sometimes) bigger sized code okay.

I think that Larrabee will also suffer from decoding bandwidth and there isn't much to do about it until someone wins with a better architecture or Intel (as the monopolist in this case) will move to another architecture.

Actually I can also see how hard it is to move to another arch. (remember Itanium?), I really see that some day (20+ years) x86 will get so old that it will be scrapped.
Post 26 Dec 2009, 18:56
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Borsuc



Joined: 29 Dec 2005
Posts: 2466
Location: Bucharest, Romania
Borsuc
128 bits per EVERY instruction sounds absolutely wasteful. What about immediate constants? Or do any other instruction pad itself with zeros. bleh!

also size optimization > performance optimization, unless we're in a heavy-duty application, which are the minority. Those applications can use Larabee anyway, which can use a different arch (after all it's not part of the normal CPU general-execution unit).

But having such a waste of memory for most non-demanding programs out there (not threaded also, since they don't have perf. bottleneck), that's gah. I seriously hope it will never happen.
Post 26 Dec 2009, 19:15
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DustWolf



Joined: 26 Jan 2006
Posts: 373
Location: Ljubljana, Slovenia
DustWolf
Madis731 wrote:
Actually I can also see how hard it is to move to another arch. (remember Itanium?), I really see that some day (20+ years) x86 will get so old that it will be scrapped.


I think we will much sooner switch PCs for other devices than we will switch CPU architectures within a PC.

Besides, that may not really be such a bad thing. As much as I believe a PC is something so flexible that a well designed system could run everything you need automated in a house using a single PC, I also see the role of the desktop PC as the office workhorse to be used with a bloated system for anything you come across as just wrong. Having a PC-based Linux server per building and running everything else on embeddeds seems so much cleaner.

And that creates a market for efficient and convenient embedded solutions coexisting with the PC as well.
Post 27 Dec 2009, 02:11
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Madis731



Joined: 25 Sep 2003
Posts: 2141
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Madis731
@Borsuc: I have been thinking about the ballast and the waste when you try to implement a fixed-length instruction width.

What you can design is an instruction that not only will add registers A+B (and therefore waste about 100+ bits), but encode as much other operations in the other bits as possible, like selective masks and/or rotate/shift of the result and/or conditional copy/move/exchange of other registers, memory operands etc.

Then there would not be a NOP or an INC instruction, but a 128-bit macroinstruction that does all the simple instructions you need or don't need. Then there's of course the compiler or the assembler optimization issue. How do you pack the useful 128 bits of instructions into logical program flow? :S
Post 27 Dec 2009, 14:02
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
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revolution
Madis731: You are designing another Itanium! Razz
Post 27 Dec 2009, 14:56
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Borsuc



Joined: 29 Dec 2005
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Borsuc
Madis, yes that does sound like Itanium, where you get several instructions in one go (and if you have dependency, i.e you can't make it in parallel, then you put 'nops' for the other execution units).
Post 27 Dec 2009, 20:42
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DustWolf



Joined: 26 Jan 2006
Posts: 373
Location: Ljubljana, Slovenia
DustWolf
Borsuc wrote:
Madis, yes that does sound like Itanium, where you get several instructions in one go (and if you have dependency, i.e you can't make it in parallel, then you put 'nops' for the other execution units).


Which also means that the compiler has to check for dependeny like in Itanium, thus if everybody uses the CPU and you made the compiler, you own the world.

...how Intel.
Post 27 Dec 2009, 21:32
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Madis731



Joined: 25 Sep 2003
Posts: 2141
Location: Estonia
Madis731
Smile

The 'good compiler means everything'-principle also works for TTA-CPU. Its like rearranging the micro-instructions (when you think of an x86 Core 2+) in your assembly.

I think Itanium is more like ARM and less like TTA.

Actually yesterday, when I was playing with LogiSim and planning my register access I "reinvented" register renaming.
I think I now understand the concept. What is really clever is when you tried to do everything in one clock, you would end up in a loop. Lets take INC EAX. When you try to write it back, it immediately starts a new cycle, where it reads a new value.
What you do (as a designer), is make up an EAX'-register (and EAX'' etc.), where you write the result of EAX+1 => EAX'. Now the artificial barrier stops you from overwriting the original EAX and you can copy the value back into EAX on the next clock.
...or not! Smile You can also tell all the ALU-s and XMM-units that "Hey, the new EAX sits in EAX' now" and the next instruction takes it from there...

I think register-renaming also works in cases like FXCH st0,st6.
Post 28 Dec 2009, 12:11
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revolution
When all else fails, read the source


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revolution
Itanium <> ARM. Indeed, so different that it is hard to imagine any meaningful way to compare them.
Post 28 Dec 2009, 14:47
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