I am still not sure if I understand the basic archite of todays PC correctly. Please let me know if my description is right, and what I missed:

There are two buses going from CPU: memory bus and I/O bus (for in/out). Memory bus goes to northbridge, from where it connects to RAM, Video RAM, SMRAM, or southbridge. I/O bus goes directly to southbridge. Southbridge connects to all the rest (SMBus, LPC, PCI bus, SATA, IEEE1394, USB, LAN, Express Card, etc...). Besides, there is a parallel (fast) DMA bus which connects selected devices (video RAM, RAM, HDD controller, soundcard?), but it doesn't connect to CPU (it is controlled via southbridge).

Right? Did I miss something important? Some vocabulary is wrong?

From the CPU the I/O and memory buses use the same data and address lines. Only the control lines are different.

And the northbridge/southbridge thing is only valid for some mobos. CPUs with internal memory controllers don't have the same architecture. The Corei7's and the later AMD cores are NUMA based. Look for QPI (Intel) and Hypertransport (AMD) to see how the NUMA systems are constructed.

Isn't this accurate (source)?

It is for some mobos, but not for either the older (pre-pentium) mobos or the latest (X4, and Nehalem) mobos.

Hi,

The richness of these replies and the profound insight you all display makes my heart ache. No offense intended.

While I don't intend to sound too smart for my own good, or claim to be exactly right, I have been wondering about these things for the sake of awful timing issues and picking up the documentation I could I did figure some things out. So let me try...



The memory interface is not a bus! The word "bus" is not a generic name for a bunch of wires, it tends to be a bunch of wires connected in the same way to multiple devices. The SCSI bus being the most graphic and clearly observable example of this. On a bus, the transmitting device identifies it's destination, transmits it's message to everybody and then only the destination device accepts it.

The memory is connected far more point-to-point-ly than this. The multiple memory modules do not connect to the same wires, but to different ones, all nicely multiplexed so that the CPU can select the exact destination and send it's command only there.



Hmm... no.

Some things are different between Intel and AMD architectures (on Intel there is a communications protocol between the memory controller aka northbridge and the processor, whereas on AMD this memory controller and all the in-between circuitry is embedded in the processor).

The IBM PC spec defines the chipset as an array of micro-controllers (hence the name), which take care of the electrical interface and protocol adaptations to allow the connection of computer peripherals (keyboard, mouse, serial port, that sort of thing) physically to the CPU I/O pins (and these are always accompanied with the Clock pins, which do not appear on any of the diagrams, but ensure that the CPU waits for the slow micro-controllers).

External memory modules, such as the Video RAM, BIOS and memory on other add-in cards are mapped into the CPU's memory space by these micro-controllers using a currently undisclosed protocol to communicate with some of the circuity on the CPU side of the memory controller (so that when the CPU writes to what it believes to be memory, the hardware redirects this data into the external memory). I think this circuitry is called "the crossbar switch" although this may be AMDspeak. I also think that there is no caching involved in this communication, thus whenever writing to this mapped external memory, the CPU does nothing until the package is delivered (meaning that when your couple-GHz CPU is talking to a device behind remanents of the old ISA bus, it is effectively an 8 MHz CPU, if not worse).

ALL of these micro-controllers are still connected via the I/O pins to the CPU, so for example when reading from the BIOS chip (<1MB memory area), it will be by default configured to let you read from the memory shadow (it's runtime copy), but when you want to read from the actual chip (to get the original program), you have to send a special I/O signal to it, so that it reconfigures the interface to let you.

All of the interfaces you describe each have a special way of functioning and I don't know them all:
* The PCI bus for starters is not technically a bus (we call it that way because it preforms a similar function as the ISA bus and is it's successor), but is more like a network, where the PCI controller (which the CPU actually talks to via I/O?) sets up communication with each of the devices using a sophisticated protocol, which sets up everything from your DMA* (which is no more magical than simply the PCI cards explaining to the controller that they need some memory accessed and getting it) to IRQs to I/O communication. To be clear there are no extra channels here, the PCI controller is just another one of those micro-controllers in the chipset.
* The SMBus for example has it's controller connected to the CPU in a simmilar I/Oy fashion, but instead use the SMBus protocol also known as I2C protocol (which's two wire protocol is accessible to the CPU via the two I/O ports you can see in your device manager).
* etc

Separating the chipset into a northbridge and a southbridge is generally just Intelspeak for separating two major parts of a typical chipset on their motherboard: The memory controller and everything else. Where this arrangement could not possibly apply to AMD setups where the memory controller is embedded in the CPU die, many motherboard or chipset manufacturers (actually I think all except Asus?) tend to implement the chipset as two big chips which contain all the standard micro-controllers you'd expect to find in a modern ATX PC. You will notice that there are many other chips on a modern motherboard without such fancy names, so don't put so much weight on these. To your typical gamer these things are important simply because the two big chips use a fast standard physical interconnect in which communication between the various components is artificially encapsulated (for example HyperTransport; as to avoid the insane number of wires that would otherwise have to be on the board, I guess), and being fast, hardware supporting it must be appropriately clocked and powered, and thus run very hot, and thus needs to have fancy cooling artifacts glued to it.

Think that covers your points? I invite more discussion on this though, I love to learn more about this.

* = EDIT: Okay... the DMA controller is a seperate chip and it was around from the days of the dinosa... er, ISA. It's a trivial micro-controller that can do a byte-based memcopy(); for you without using the CPU. Being a micro-controller also means it's Slow, but back in the days it was good as it was asynchronous. Check your device manager and you will soon realize that nothing uses it, other than your floppy disk controller, which is not famed for it's speed.

LP,
Jure

ugh... too much information at once. Let me pursue just one point for now: (and I am talking about Intel archictere in case when AMD differs, ignoring latest "NUMA" stuff)


AFAIK the separation is mostly about speed. CPU-to-northbridge is supposed to be fast (hence also access to RAM, Video RAM, ?BIOS ROM?, SMRAM) while northbridge-to-southbridge link is slow, and so it should be used only for occasional sending of data codes.

From your explanation it would seem that there is no CPU-northbridge-southbridge "backbone", but instead chipset is more like point-to-point network consisting of CPU, memory controller (linked to various RAMs and ROMs), and other chips. That would mean I/O communication with all chips besides northbridge / memory controller, and also what we know (from CPU point of view) as memory-mapped devices, isn't really routed through northbridge, as we see on diagrams. Is this what you was saying?

Naturally because on Intel boards, the northbridge aka the memory controller is connected using FSB, which is deemed fast and the southbridge aka everything else is connected the good old fashioned way, sometimes even as devices on a PCI bus (133 MHz, 32bit).



Hmm... well the northbridge often also contains, say on Intel boards, the circuitry that decodes the FSB interface into whatever it is the southbridge uses to communicate, so yes and no. Physically yes, in terms of who is talking to who, no (there is no routing and processing done by the northbridge, only decoding). And the northbridge is no unified entity beyond the point that it is one chip and may use one encapsulation protocol to communicate with other chips. Same applies to the southbridge.

On AMD + nForce motherboards, the CPU, the "northbridge" and the southbridge, speak the same language: HyperTransport. There the communication is physically routed (in the sense of HyperTransport routers) trough the "northbridge", though there isn't anything in the southbridge talking to the "northbridge", just the CPU. VIA's motherboards use much the same thing, though they have decided to market their HyperTransport link as "V-Link". Both implementations run rather hot.

I use quotes above because on AMD motherboards, there is no memory controller in this "northbridge". Due to the bandwidth capacity you speak of, many motherboards include circuitry for managing the PCI-Express communication on the northbridge. Since that chip is above and thus closer to the CPU (per the ATX standard) than the southbridge, it makes sense for it to have the faster interface (less trouble with EMI and the likes).

Obviously, these speed, and north/south issues have nothing to do with architecture and everything to do with the layout of the motherboard (and the compatible chips available to them). Naturally that is why they are a little different with each motherboard manufacturer.

EDIT: Upon reading up a bit on what troubles these motherboard manufacturers, the idea is that there isn't as many wires on the motherboard and pins on the CPU, as there are needed to connect everything (all the peripherals and micro-controller functions), thus the FSB, HyperTransport and other such "nonsese" is used to keep the pin count reasonable. Naturally this reduction means that the CPU couldn't talk to all these devices at the same time (or more practically, one after the other, quickly, faster than the transport bandwidth allows), thus the chipset and motherboard makers try to pick combinations with the biggest bandwidth, to suit this rapid I/O demand.

LP,
Jure