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Index > Main > sub rdx,$2B6109100 out of range, why?

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Azu



Joined: 16 Dec 2008
Posts: 1159
Azu
This compiles and runs
Code:
          sub     rdx,qword[v2B6109100]
retf
v2B6109100     dq      $2B6109100    



This gives out of range error
Code:
              sub     rdx,$2B6109100
retf    



Why? I am sure I entered 64bit mode successfully or the first one wouldn't be working.. but then shouldn't the second one work? Confused
Post 25 Jul 2009, 04:12
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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
There is no such instruction (sub r64, imm64). You may want to read this: http://x86asm.net/articles/x86-64-tour-of-intel-manuals/index.html
Post 25 Jul 2009, 04:30
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Azu



Joined: 16 Dec 2008
Posts: 1159
Azu
http://x86asm.net/articles/x86-64-tour-of-intel-manuals/index.html wrote:
Code:

Table 3-4. Effective Operand- and Address-Size Attributes in 64-Bit Mode
L Flag in Code Segment Descriptor      1       1       1       1       1       1       1       1
REX.W Prefix       0       0       0       0       1       1       1       1
Operand-Size Prefix 66H    N       N       Y       Y       N       N       Y       Y
Address-Size Prefix 67H    N       Y       N       Y       N       Y       N       Y
Effective Operand Size     32      32      16      16 ---->64<----   64 ---->64<----   64
Effective Address Size    64      32      64      32 ---->64<----   32 ---->64<----   32    


It looks like I should be able to do it with a prefix or something?
Post 25 Jul 2009, 04:48
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bitRAKE



Joined: 21 Jul 2003
Posts: 3035
Location: vpcmipstrm
bitRAKE
10 bytes...
Code:
push -$56C21220
pop rax
lea rdx,[rdx+rax*8]    
...nah, has to be memory or a register source for 64bit.
Post 25 Jul 2009, 05:33
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bitRAKE



Joined: 21 Jul 2003
Posts: 3035
Location: vpcmipstrm
bitRAKE
Not without merging more functionality, imho.
Code:
use64

bitRAKE:push -$56C21220
 pop rax
     lea rdx,[rdx+rax*8]

Azu:     mov     rax,(1 shl 64)-$2B6109100
   add     rax,rdx

display $30 - Azu - Azu + $ + bitRAKE    
...looks like yours is three bytes longer, but one less instruction.
Post 25 Jul 2009, 07:51
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Azu



Joined: 16 Dec 2008
Posts: 1159
Azu
aaaa where'd my post go Sad
Post 25 Jul 2009, 07:54
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asmcoder



Joined: 02 Jun 2008
Posts: 784
asmcoder
[content deleted]


Last edited by asmcoder on 14 Aug 2009, 14:48; edited 5 times in total
Post 25 Jul 2009, 13:58
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Borsuc



Joined: 29 Dec 2005
Posts: 2466
Location: Bucharest, Romania
Borsuc
he was talking about sub, not mov
Post 25 Jul 2009, 14:52
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asmcoder



Joined: 02 Jun 2008
Posts: 784
asmcoder
[content deleted]


Last edited by asmcoder on 14 Aug 2009, 14:48; edited 1 time in total
Post 25 Jul 2009, 14:59
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Azu



Joined: 16 Dec 2008
Posts: 1159
Azu
asmcoder wrote:
Quote:
add rax,0x555555555555

LOL?
is that a joke? why it doesnt work?
so i do have to load another GPR to make add/sub? it suck
I think the specification is broken, someone needs to fix it or something Sad
Post 25 Jul 2009, 20:14
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Borsuc



Joined: 29 Dec 2005
Posts: 2466
Location: Bucharest, Romania
Borsuc
No, there simply is no instruction encoding for it.

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Previously known as The_Grey_Beast
Post 25 Jul 2009, 21:19
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Azu



Joined: 16 Dec 2008
Posts: 1159
Azu
The instruction encodings aren't part of the specification? Confused
Post 25 Jul 2009, 23:24
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