hi, i'm writing an operating system (FASM) to be compatible with protected and unreal mode 32-64 bit. it is designed to be an educational OS with lots of run-time informations and debugging. at the moment it is in 2nd-stage boot loader development and i want tu upload it on Christoffer Bubach homepage, but i've seen that i can't make an account to log in. if someoane knows what can i do i'll be most gratefull.

What is it that you want help with? The coding? The design? The assembler? The x86 instructions? Or the website you mention?

i wan't to post it on the asmhackers.net website, but i'm still working. and i have a few questions about coding and design.

Okay, but this is not that site, perhaps you can try emailing the webmaster of that site to ask for help. Okay, shoot your Q's here, but don't be vague, be specific and don't be afraid to post code to backup your Q's.

first of all, i have modified mhc archiver, to fit my os design and i've tried to compres some images (bmp format) wich integrates into 2nd stage loader because i'm displaying them in section 'about OS'.
i don't know if it is good what i'm doing, because i have to wait a lot (when it's working on real machine, not virtual machine) and that is because the integrated compressed images are too big (about 100k, but there were about 300k initially) .

- i have these 2 lines below just at the end of code, and there are a result from the same file name but in bmp uncompressed format

in_autor: file 'autor.arh' ;pointer la autor
in_logo: file 'logo.arh' ;pointer la logo

i'll post the images and some screen-shots

Yes, I'm developing my own GUI-based RTOS, GreenOmega 64.
I just like to write my own programs and really want to try it out.
But...

Well, shoot. I'm still looking into the source codes.

Now, I can't find one thing that I was really looking for: A driver source code
for a new kind of DRAM controller. Yes, a XDR controller.
I was kinda wanting to prepare my GreenOmega 64 OS for
a new breed of AMD Phenom (containing Rambus XDR controller PHY
located at end of Level 3 cache.) so that way this OS' kernel will correctly
request for Serial ID (for each XDR chips or a XDIMM module) for the ID information and also to page the size of the XDRs so it could, in fact, activate and map it for the temporary storage (like it would with existing DDR+ memories.)

Plus, I already have looked into PS3 Linux (for skeleton code, that I'm focusing at, for Rambus XDR DRAM controller - but yet, nothing is found. If it's coded in 64-bit PPC, I will have to translate it into x86 codes anyways. That way the newest Phenom CPU will be able to activate both its own XDR controller and either DDR3 or XDR memory mounted on motherboard.)