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Index > Main > SSE4 white paper is now available from Intel

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revolution
When all else fails, read the source


Joined: 24 Aug 2004
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revolution
Post 22 Nov 2006, 12:40
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Tomasz Grysztar



Joined: 16 Jun 2003
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Tomasz Grysztar
Of course opcodes are yet confidential?
Post 22 Nov 2006, 12:48
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vid
Verbosity in development


Joined: 05 Sep 2003
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vid
well... both FASM and YASM already have SSSE3 / SSE4 support
Post 22 Nov 2006, 12:50
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Garthower



Joined: 21 Apr 2006
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Garthower
Interesting expansions. Commands for work with strings can be very useful. I think, that it's necessary to add support of these commands in FASM.
Post 22 Nov 2006, 12:51
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Tomasz Grysztar



Joined: 16 Jun 2003
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Tomasz Grysztar
vid: SSSE3 is not SSE4.
Post 22 Nov 2006, 12:55
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vid
Verbosity in development


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vid
so this SSE4 is *not* SSSE3? some real SSE4 this time? wow
Post 22 Nov 2006, 14:26
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smiddy



Joined: 31 Oct 2004
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smiddy
Hi Tomasz, here ya go: http://www.intel.com/design/processor/manuals/253667.pdf
&
http://developer.intel.com/design/processor/manuals/253666.pdf

Whoops, a quick look and those instructions from the white paper are not in here, bummer!
Post 22 Nov 2006, 17:06
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17632
Location: In your JS exploiting you and your system
revolution
Sorry if the title confused people. I didn't mean to suggest that the opcodes had been published. Maybe a moderator can change the title to "SSE4 white paper is now available from Intel".

Anyhow the new instructions are not particularly exciting unless you happen to be programming in a specific field that can make use of them. The dot product and rounding instructions look to be the most useful. Maybe the string functions that mentions ZLIB as benefitting could also be worthwhile.
Post 22 Nov 2006, 23:06
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r22



Joined: 27 Dec 2004
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r22
Packed multiply with 32bit and 64bit is great, something I've personally wanted.

CRC32 opcode sounds like it would be very useful. I'll hold my final judgements until the performance and latency data is available.

I can see why dot product is being added, might as well already have it in the architecture when we start seeing CPU/GPU combo processors in a few years.

WHAT I STILL WANT:
PLB/PLW/PLD/PLDQ packed load byte/word/dword/qword - replacing the addresses stored in the XMM register with the data at those addresses.
Parallel random access to memory data would rock. Imagaine being able to do multiple look ups on multiple LUTs at the same time that would be incredibly useful.
This combined with packed multiply and packed add for the address would be so cool.

Shame I don't design microprocessors :/
Post 24 Nov 2006, 06:27
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Maverick



Joined: 07 Aug 2006
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Maverick

r22 wrote:
Shame I don't design microprocessors :/

You can. Get a FPGA board and learn Verilog.

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Fabio
Post 24 Nov 2006, 07:52
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MCD



Joined: 21 Aug 2004
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MCD
Maverick wrote:

r22 wrote:
Shame I don't design microprocessors :/

You can. Get a FPGA board and learn Verilog.

sure, but not everyone has time/money to do so

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MCD - the inevitable return of the Mad Computer Doggy

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Post 29 Dec 2006, 07:21
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f0dder



Joined: 19 Feb 2004
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Location: Denmark
f0dder
Hmm, CRC32 opcode seems pretty silly to me - it's pretty blazing fast already with a LUT implementation. Where would this be useful? Outside of networking, where it really should be moved onto the NIC. Ok, intel mentions iSCSI and RDMA, but ho humm.
Post 29 Dec 2006, 12:24
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comrade



Joined: 16 Jun 2003
Posts: 1137
Location: Russian Federation
comrade
CISC all the way!
Post 31 Dec 2006, 17:34
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