Multi-byte NOP instructions support

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Hunter

Joined: 07 Jun 2006
Posts: 41

Hunter

Hi Tomasz!
Will FASM support multi-byte NOP instructions? For example:
NOP r/m16
NOP r/m32
(See IA-32 Intel® Architecture Software Developer’s Manual, Volume 2B:Instruction Set Reference, N-Z, page 4-4, NOP—No Operation).

10 Jul 2006, 16:31

vid
Verbosity in development

Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia

vid

there was already thread about this i think. try searching before posting

10 Jul 2006, 18:30

LocoDelAssembly
Your code has a bug

Joined: 06 May 2005
Posts: 4633
Location: Argentina

LocoDelAssembly

Can you post the thread where it appears? All what I found about NOP is not related to this.

10 Jul 2006, 21:08

Hunter

Joined: 07 Jun 2006
Posts: 41

Hunter

I also not found any related topics.
Tomasz, what do you think about this problem?

11 Jul 2006, 10:31

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 7848
Location: Kraków, Poland

Tomasz Grysztar

Perphaps vid this means threads like this: http://board.flatassembler.net/topic.php?p=23957#23957 ?

11 Jul 2006, 14:57

vid
Verbosity in development

Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia

vid

yup - you meant something else? (sorry, i don't have those manuals..)

11 Jul 2006, 16:45

Hunter

Joined: 07 Jun 2006
Posts: 41

Hunter

Tomasz, I've seen this link, but there are another opcodes.
NOP r/m16 ; 0F 1F /0
NOP r/m32 ; 0F 1F /0
it's official opcode from Intel manual.

11 Jul 2006, 16:57

LocoDelAssembly
Your code has a bug

Joined: 06 May 2005
Posts: 4633
Location: Argentina

LocoDelAssembly

I tested the opcodes of that manual on my Athlon64 and no invalid opcode exception was generated Very Happy

OllyDbg does not recognizes them though

11 Jul 2006, 18:55

vid
Verbosity in development

Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia

vid

does it touch memory region, or what is it for? just faster padding?

11 Jul 2006, 20:18

mattst88

Joined: 12 May 2006
Posts: 260
Location: South Carolina

mattst88

http://www.codecomments.com/message321021.html

11 Jul 2006, 20:35

LocoDelAssembly
Your code has a bug

Joined: 06 May 2005
Posts: 4633
Location: Argentina

LocoDelAssembly

Here it is what Hunter is telling:

11 Jul 2006, 22:05

LocoDelAssembly
Your code has a bug

Joined: 06 May 2005
Posts: 4633
Location: Argentina

LocoDelAssembly

Code:

format PE GUI 4.0

macro nop src
{
local ..lea
  if ~src eq
    db $0F
    ..lea: lea eax, src
    store $1F at ..lea
  else
    nop
  end if
}
irps instr, noP nOp nOP Nop NoP NOp NOP {macro instr src \{nop src\}}

db $66
NOP
NOP DWORD [EAX]

; Due to the optimization of FASM, 00H byte displacement will not be encoded
NOP DWORD [EAX + 01H]
NOP DWORD [EAX + EAX*1 + 01H]
db $66
NOP DWORD [EAX + EAX*1 + 01H]

NOP DWORD [dword EAX + 00000000H]
NOP DWORD [dword EAX + EAX*1 + 00000000H]
db $66
NOP DWORD [dword EAX + EAX*1 + 00000000H]

int3

At least on my CPU reaches int3 without problems.

11 Jul 2006, 22:38

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 7848
Location: Kraków, Poland

Tomasz Grysztar

66 90 is "XCHG AX,AX" Wink

12 Jul 2006, 07:14

Hunter

Joined: 07 Jun 2006
Posts: 41

Hunter

Ok, Tomasz, could you add muti-byte NOP support to FASM? Wink

12 Jul 2006, 09:59

RedGhost

Joined: 18 May 2005
Posts: 443
Location: BC, Canada

RedGhost

hmm, $60 $90 is infact xchg ax, ax

xchg eax, eax generations $90, i did not know this, xchg ebx, ebx or related would be 2 bytes but xchg eax, eax is 1

learn something new everyday Smile

_________________
redghost.ca

12 Jul 2006, 12:08

LocoDelAssembly
Your code has a bug

Joined: 06 May 2005
Posts: 4633
Location: Argentina

LocoDelAssembly

http://board.flatassembler.net/topic.php?p=40777#40777 Smile

12 Jul 2006, 13:29

Reverend

Joined: 24 Aug 2004
Posts: 408
Location: Poland

Reverend

RedGhost: All "xchg eax, xxx" are one-byte long. That's true for all xchgs with eax as operand. Other variations are two-byte long

14 Jul 2006, 10:16

MazeGen

Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia

MazeGen

See also U.S. Patent 5,701,442. It covers opcodes 0F18-0F1F.

24 Jul 2006, 07:51

vid
Verbosity in development

Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia

vid

MazeGen wrote:

See also U.S. Patent 5,701,442. It covers opcodes 0F18-0F1F.

That USA crap is terrible? How can you people live there?!?

24 Jul 2006, 08:15

UCM

Joined: 25 Feb 2005
Posts: 285
Location: Canada

UCM

vid: no kidding.
How can you patent an instruction?

24 Jul 2006, 13:26

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