Hello!

Can anybody explain me the FASM syntax for using sign extension feature for imm8 arguments?
Example:
I need to add a number 0x20 to BX register.
I use a command: ADD BX, 0x20
After compilation I can see that FASM generated a word from 0x20 number by adding an extra 0x00 to the command. The situation is even worse if I'm using r/m32 as a destination - three extra 0x00.
According to Intel manual there should be a possibility to automatically sign extend imm8 argument if the destination is word or double word. So after the compilation there wouldn't be any extra 0x00.
What syntax should I use implement this capability with FASM?

fasm by default generates the shorter code (the one with imm8), unless you force the full 16-bit immediate size by writing ADD BX, WORD 0x20.

Yes, you're right. It works fine for 0x20, but doesn't work for 0xFF. It still generates extra zeroes.

As you said, imm8 is sign-extended, so this "sign extension" feature can't work for ADD BX, 0xFF (0x00FF), because it would be ADD BX, 0xFFFF then.

1. "Intel says" it should work, though it produces the same result as SUB BX, 1 with reduced command length
2. "Intel says" it should also work with such commands as XOR, like
XOR BX, 0xE8, giving the same result as XOR BX, 0xFFE8 but one byte shorter (3 bytes shorter with EBX). And I can't replace this command with anything else having the same result and the same length.

Or is it just my wrong interpretation of what does "Intel say"?

"XOR BX, 0xE8" only affects the bits in BL and "XOR BX, 0xFFE8" affects BH and BL.Clearly it isn't for far the same.

[edit]Sorry, I misunderstood what you said?[/edit]

When you write "XOR BX, 0xFFE8" fasm generates the shortened form, just like you need. Same with "ADD BX,0FFFFh" and "ADD BX,-1". And "SUB BX,1" will be short form also, so there is no advantage in using "ADD BX,-1" instead of it.

Cool