Index
> OS Construction > PCI Express |
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DimonSoft 02 Apr 2020, 10:57
It has a separate page for that: https://wiki.osdev.org/PCI_Express And it has the name of specification to google for in its references section.
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02 Apr 2020, 10:57 |
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Fulgurance 02 Apr 2020, 11:46
...Hum yes, i have already say i have seen this link, but it's not very full documentation.
It's mentionned: This extended configuration space *cannot* be accessed using the legacy PCI method (through ports 0xCF8 and 0xCFC). Okay... but what way i need to use ? |
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02 Apr 2020, 11:46 |
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Fulgurance 02 Apr 2020, 14:59
Nobody?
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02 Apr 2020, 14:59 |
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DimonSoft 02 Apr 2020, 15:23
Fulgurance wrote: ...Hum yes, i have already say i have seen this link, but it's not very full documentation. https://wiki.osdev.org/PCI_Express wrote: The PCI Express bus extends the Configuration Space from 256 bytes to 4096 bytes. This extended configuration space *cannot* be accessed using the legacy PCI method (through ports 0xCF8 and 0xCFC). Instead, an #Enhanced Configuration Mechanism is provided. Emphasis mine. And note the References section that gives the name of the specification which is the original document for this page and any other source you might find. |
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02 Apr 2020, 15:23 |
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Fulgurance 02 Apr 2020, 15:31
Yes i have already seen this link, but it's just link to this page, but page don't mention how to send this data
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02 Apr 2020, 15:31 |
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N-LG 02 Apr 2020, 15:52
the answer is in the page but needs to master the ACPI to understand it. find out about ACPI before trying to go any further in the pci express. knowledge of standard pci is sufficient to be able to detect and configure peripheral devices in pci express
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02 Apr 2020, 15:52 |
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Fulgurance 02 Apr 2020, 16:44
Okay, i'm going to read that. Thanks. I come to you if i have other questions.
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02 Apr 2020, 16:44 |
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Fulgurance 02 Apr 2020, 20:38
Are you sure ACPI is mandatory ?
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02 Apr 2020, 20:38 |
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DimonSoft 02 Apr 2020, 20:51
So, reading specs is not an option, I guess?
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02 Apr 2020, 20:51 |
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N-LG 02 Apr 2020, 22:21
if you want clarification on the subject I advise you to contact the authors of the page on the forum osdev.org
I have the impression that you are asking questions on many different subjects, I suggest you to focus on one subject at a time read the documentation, even if like me it is not in your language of birth. bone programming is very complicated and you will not necessarily find a specialist ready to help you a lot. |
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02 Apr 2020, 22:21 |
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Fulgurance 02 Apr 2020, 23:17
I asking because i have finished to understand the previous subjects. I have already coded what i talk into topic.
And it's forum, yes i ask question... Normal, i coding OS... And if i ask question, it's because some documentation isn't very clearfull... I search usefull reply, thanks. |
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02 Apr 2020, 23:17 |
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FlierMate 12 Jan 2022, 14:25
I read in UHCI documentation, it says:
Quote: This section describes the block of USB registers that are located in normal I/O space. The “base” portion of the I/O It is nice to know that " legacy PCI method (through ports 0xCF8 and 0xCFC)", finally the port addresses are revealed. Supposedly I want to connect HID mouse (USB 1.1), should I use PCI or PCI-Express? I plan to emulate through i386 QEMU. |
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12 Jan 2022, 14:25 |
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FlierMate 12 Jan 2022, 18:52
I have finished the PCI enumeration part, with reference to OSDev article.
However, QEMU (i386) did not detect my USB mouse although I already pass the command line argument to enable USB and add USB mouse as device. The enumerated PCI devices were: * Network controller (Class 02) * Display controller (Class 03) * Host Bridge (Class 06) * ISA Bridge (Class 06 Subclass 01) What's wrong then?
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12 Jan 2022, 18:52 |
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FlierMate 12 Jan 2022, 23:08
FlierMate wrote:
Fixed! If class ID = 6 (Bridge), then need to enumerate through function 00h to 07h.....
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12 Jan 2022, 23:08 |
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