AVX-512 transitions

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Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8359
Location: Kraków, Poland

Tomasz Grysztar 17 Jan 2020, 21:22

A really interesting article about AVX-512 performance (with experimental approach) posted today:
Gathering Intel on Intel AVX-512 Transitions.

17 Jan 2020, 21:22

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 18 Jan 2020, 03:14

I think the outcome there is if you need top performance then execute the wide AVX instructions in batches, and not intersperse them amongst other code.

18 Jan 2020, 03:14

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8359
Location: Kraków, Poland

Tomasz Grysztar 26 May 2020, 16:22

Another amazing article: AVX-512 Mask Registers, Again.

26 May 2020, 16:22

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 27 May 2020, 05:08

Tomasz Grysztar wrote:

Another amazing article: AVX-512 Mask Registers, Again.

So we need to save the FPU state before using AVX-512? And the opposite, we need to save the AVX-512 state before using the FPU?

What happens if I mix FPU instructions with AVX-512 instructions in a single stream? Does the OS have to do a context save/restore each time the new instruction type is executed? So not only do we get a forced down-clock, we also get a forced context change. Yuck.

27 May 2020, 05:08

Furs

Joined: 04 Mar 2016
Posts: 2565

Furs 27 May 2020, 15:41

revolution wrote:

So we need to save the FPU state before using AVX-512? And the opposite, we need to save the AVX-512 state before using the FPU?

What happens if I mix FPU instructions with AVX-512 instructions in a single stream? Does the OS have to do a context save/restore each time the new instruction type is executed? So not only do we get a forced down-clock, we also get a forced context change. Yuck.

That's not what I understood. It's about the physical register space being shared. Which is quite large (128 registers) due to renaming.

So you'll simply have less x87 registers available for renaming if you also use mask registers (and vice-versa). This is a performance loss, of course, but far different than what you think (context switches) and is completely transparent to software.

27 May 2020, 15:41

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20451
Location: In your JS exploiting you and your system

revolution 28 May 2020, 11:18

Furs wrote:

That's not what I understood. It's about the physical register space being shared. Which is quite large (128 registers) due to renaming.

So you'll simply have less x87 registers available for renaming if you also use mask registers (and vice-versa). This is a performance loss, of course, but far different than what you think (context switches) and is completely transparent to software.

Okay, yes. I guess that makes sense. Thanks for the explanation.

28 May 2020, 11:18

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